/*
 * Copyright     :  Copyright (C) 2021, Huawei Technologies Co. Ltd.
 * File name     :  pcie5_core_addr_define.h
 * Project line  :  Platform And Technologies Development
 * Department    :  CAD Development Department
 * Version       :  1.0
 * Date          :
 * Description   :  PCIE Controller 5.0  Version 200
 * Others        :  Generated automatically by nManager V5.1
 * History       :  2021/01/07 09:08:21 Create file
 */

#ifndef PCIE5_CORE_ADDR_DEFINE_H
#define PCIE5_CORE_ADDR_DEFINE_H

/* HIPCIEC50_TOP_REG Base address of Module's Register */
#define CSR_HIPCIEC50_TOP_REG_BASE (0x5C000)

/* **************************************************************************** */
/*                      HIPCIEC50_TOP_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_INT_SET_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x0) /* apb timeout interrupt set \
                                                                                          */
#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_INT_MASK_REG \
    (CSR_HIPCIEC50_TOP_REG_BASE + 0x4) /* apb timeout interrupt mask */
#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_INT_STATUS_REG \
    (CSR_HIPCIEC50_TOP_REG_BASE + 0x8) /* apb timeout interrupt status */
#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_INT_RO_REG \
    (CSR_HIPCIEC50_TOP_REG_BASE + 0xC) /* apb timeout interrupt status */
#define CSR_HIPCIEC50_TOP_REG_PCIE_TOP_LOCAL_INT_EN_NI_REG \
    (CSR_HIPCIEC50_TOP_REG_BASE + 0x10) /* pcie top local interrupt selection for ni */
#define CSR_HIPCIEC50_TOP_REG_PCIE_TOP_LOCAL_INT_EN_CE_REG \
    (CSR_HIPCIEC50_TOP_REG_BASE + 0x14) /* pcie top local interrupt selection for ce */
#define CSR_HIPCIEC50_TOP_REG_PCIE_TOP_LOCAL_INT_EN_NFE_REG \
    (CSR_HIPCIEC50_TOP_REG_BASE + 0x18) /* pcie top local interrupt selection for nfe */
#define CSR_HIPCIEC50_TOP_REG_PCIE_TOP_LOCAL_INT_EN_FE_REG \
    (CSR_HIPCIEC50_TOP_REG_BASE + 0x1C) /* pcie top local interrupt selection for fe */
#define CSR_HIPCIEC50_TOP_REG_APB_WR_LAST_ADD_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x20)   /* APB WRITE LAST ADDR */
#define CSR_HIPCIEC50_TOP_REG_APB_WR_TIMES_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x24)      /* APB WRITE NUMBERS */
#define CSR_HIPCIEC50_TOP_REG_APB_TIMER_CTRL_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x30)    /* apb timeout timer control */
#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_INFO_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x34)  /* apb timeout status */
#define CSR_HIPCIEC50_TOP_REG_APB_TIME_OUT_NUM_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x38)  /* apb timeout number */
#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_RDATA_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x3C) /* APB rdata for timeout */
#define CSR_HIPCIEC50_TOP_REG_PEH_AXI_USER_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x100)   /* IEP axi user */
#define CSR_HIPCIEC50_TOP_REG_PEH_AXI_USER_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x104)   /* IEP axi user */
#define CSR_HIPCIEC50_TOP_REG_PEH_AXI_USER_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x108)   /* IEP axi user */
#define CSR_HIPCIEC50_TOP_REG_PEH_AXI_USER_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x10C)   /* IEP axi user */
#define CSR_HIPCIEC50_TOP_REG_PEH_AXI_USER_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x110)   /* IEP axi user */
#define CSR_HIPCIEC50_TOP_REG_IEP_TC_ID_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x120)      /* iep tlp tc_id */
#define CSR_HIPCIEC50_TOP_REG_IEP_TC_ID_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x124)      /* iep tlp tc_id */
#define CSR_HIPCIEC50_TOP_REG_IEP_TC_ID_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x128)      /* iep tlp tc_id */
#define CSR_HIPCIEC50_TOP_REG_IEP_TC_ID_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x12C)      /* iep tlp tc_id */
#define CSR_HIPCIEC50_TOP_REG_IEP_TC_ID_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x130)      /* iep tlp tc_id */
#define CSR_HIPCIEC50_TOP_REG_IEP_CREDIT_CLR_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x140)   /* crdit cnt clear */
#define CSR_HIPCIEC50_TOP_REG_IEP_REG_ON_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x144)       /* peh cfgspace enable */
#define CSR_HIPCIEC50_TOP_REG_APB_RESERVE_RDATA_REG \
    (CSR_HIPCIEC50_TOP_REG_BASE + 0x148) /* apb access reserve addr , return rdata */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX0_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x800) /* peh MSI dfx0 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX0_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x810) /* peh MSI dfx0 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX0_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x820) /* peh MSI dfx0 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX0_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x830) /* peh MSI dfx0 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX0_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x840) /* peh MSI dfx0 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX1_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x804) /* peh MSI dfx1 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX1_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x814) /* peh MSI dfx1 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX1_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x824) /* peh MSI dfx1 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX1_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x834) /* peh MSI dfx1 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX1_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x844) /* peh MSI dfx1 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX2_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x808) /* peh MSI dfx2 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX2_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x818) /* peh MSI dfx2 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX2_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x828) /* peh MSI dfx2 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX2_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x838) /* peh MSI dfx2 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX2_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x848) /* peh MSI dfx2 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX3_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x80C) /* peh MSI dfx3 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX3_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x81C) /* peh MSI dfx3 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX3_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x82C) /* peh MSI dfx3 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX3_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x83C) /* peh MSI dfx3 info */
#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX3_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x84C) /* peh MSI dfx3 info */

/* HIPCIEC50_CORE_CLKRST_CTRL_REG Base address of Module's Register */
#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE (0x5E000)

/* **************************************************************************** */
/*                      HIPCIEC50_CORE_CLKRST_CTRL_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PORT_RESET_REG \
    (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x0) /* port reset */
#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PHY_RESET_REG (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x4) /* phy reset \
                                                                                                          */
#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_CORE_CLK_FLG_REG \
    (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x8) /* dfx core clk exist flag */
#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCS_SOFT_REST_REG \
    (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0xC) /* PCS and axi soft reset */
#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCIE_AP_AXI_SFT_RST_REG \
    (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x10) /* ap or axi soft reset */
#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCIE_CORE_TL_COM_SFT_RST_REG \
    (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x14) /* tl common soft reset */
#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCIE_CORE_PHY_COM_SFT_RST_REG \
    (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x18) /* phy common soft reset */
#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCIE_ICG_EN_PIPE_LANE_REG \
    (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x1C) /* pcie_icg_en_pipe_lane */
#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCIE_ICG_EN_CORE_PHY_LANE_REG \
    (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x20) /* pcie_icg_en_core_phy_lane */

/* HIPCIEC50_CORE_CTRL_REG Base address of Module's Register */
#define CSR_HIPCIEC50_CORE_CTRL_REG_BASE (0x5E000)

/* **************************************************************************** */
/*                      HIPCIEC50_CORE_CTRL_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_CORE_CTRL_REG_PORT_EN_REG (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x400)        /* port enable */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PORT_RESET_CFG_REG (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x404) /* port reset */
#define CSR_HIPCIEC50_CORE_CTRL_REG_TURBO_SIM_SEL_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x408) /* turbo sim selection */
#define CSR_HIPCIEC50_CORE_CTRL_REG_LOCAL_LOOPBACK_MODE_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x40C) /* local loopback mode selection */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_TIMING_CFG_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x410) /* PCIE SRAM timing config register */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_TIMING_CFG_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x414) /* PCIE SRAM timing config register */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_TIMING_CFG_2_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x418) /* PCIE SRAM timing config register */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_TIMING_CFG_3_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x41C) /* PCIE SRAM timing config register */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_TIMING_CFG_4_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x420) /* PCIE SRAM timing config register */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_CTRL_BUS_SP_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x424) /* PCIE SP SRAM timing config register */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_CTRL_BUS_TP_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x428) /* PCIE TP SRAM timing config register */
#define CSR_HIPCIEC50_CORE_CTRL_REG_GLB_SRAM_CTRL_BUS_EN_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x42C) /* select the value in register output to control bus */
#define CSR_HIPCIEC50_CORE_CTRL_REG_INSERT_SKP_DATA_PARITY_ERR_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x430) /* insert skp data parity error in scramble module */
#define CSR_HIPCIEC50_CORE_CTRL_REG_GLB_PCIEC_MODE_SEL_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x434) /* select pcie to up or dp and also can select pcie to rc or ep */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_RELEASE_I_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x500) /* pcie release info */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_VERSION_I_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x504)                                             /* pcie version info */
#define CSR_HIPCIEC50_CORE_CTRL_REG_APB_ECO_REG (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x50C) /* apb eco register */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PORT07_LINK_MODE_REG (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x510) /* port link mode \
                                                                                                     */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PORT815_LINK_MODE_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x514) /* port link mode */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PORT_RST_DLY_CNT_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x518) /* port soft reset or linkdown reset delay count */
#define CSR_HIPCIEC50_CORE_CTRL_REG_HILINK_INT_SET_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x51C) /* hilink interrupt set */
#define CSR_HIPCIEC50_CORE_CTRL_REG_HILINK_INT_MASK_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x520) /* hilink interrupt mask */
#define CSR_HIPCIEC50_CORE_CTRL_REG_HILINK_INT_RO_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x524) /* hilink interrupt ro */
#define CSR_HIPCIEC50_CORE_CTRL_REG_HILINK_INT_STATUS_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x528) /* hilink interrupt status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_HILINK_INT_SEL_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x52C) /* hilink interrupt type configure */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_SET_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x530) /* CORE interrupt set ni */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_MSK_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x534) /* CORE interrupt mask ni */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_STATUS_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x538) /* CORE interrupt status ni */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_RO_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x53C) /* CORE interrupt RO ni */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_SET_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x540) /* CORE interrupt set ni */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_MSK_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x544) /* CORE interrupt mask ni */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_STATUS_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x548) /* CORE interrupt status ni */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_RO_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x54C) /* CORE interrupt RO ni */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_SET_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x550) /* CORE interrupt set ce */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_MSK_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x554) /* CORE interrupt mask ce */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_STATUS_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x558) /* CORE interrupt status ce */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_RO_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x55C) /* CORE interrupt RO ce */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_SET_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x560) /* CORE interrupt set ce */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_MSK_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x564) /* CORE interrupt mask ce */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_STATUS_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x568) /* CORE interrupt status ce */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_RO_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x56C) /* CORE interrupt RO ce */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_SET_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x570) /* CORE interrupt set nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_MSK_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x574) /* CORE interrupt mask nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_STATUS_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x578) /* CORE interrupt status nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_RO_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x57C) /* CORE interrupt RO nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_SET_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x580) /* CORE interrupt set nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_MSK_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x584) /* CORE interrupt mask nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_STATUS_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x588) /* CORE interrupt status nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_RO_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x58C) /* CORE interrupt RO nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_SET_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x590) /* CORE interrupt set nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_MSK_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x594) /* CORE interrupt mask nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_STATUS_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x598) /* CORE interrupt status nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_RO_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x59C) /* CORE interrupt RO nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_SET_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x5A0) /* CORE interrupt set nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_MSK_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x5A4) /* CORE interrupt mask nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_STATUS_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x5A8) /* CORE interrupt status nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_RO_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x5AC) /* CORE interrupt RO nfe */
#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_GLB_MISC_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x700) /* phy mode and txbuf mode */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_DPTX_FIFO_THRES_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x704) /* mac cdc module tx data path fifo thres */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_0_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x708) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_1_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x70C) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_2_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x710) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_3_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x714) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_4_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x718) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_5_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x71C) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_6_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x720) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_7_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x724) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_8_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x728) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_9_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x72C) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_10_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x730) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_11_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x734) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_12_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x738) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_13_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x73C) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_14_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x740) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_15_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x744) /* mac cdc module status */
#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_CONFIG_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x74C) /* configure register for mac-cdc */
#define CSR_HIPCIEC50_CORE_CTRL_REG_LINKDOWN_RST_REG_ERN_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x750) /* linkdown_rst_reg_en */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SDS_CS_CALIB_DONE_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x754) /* pcie_sds_cs_calib_done */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SDS_PRBS_ERR_ST_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x758) /* pcie_sds_prbs_err_st */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_LINK_DOWN_RST_EN_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x75C) /* linkdown_rst_en */
#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_LINK_DOWN_CLR_PORT_EN_REG \
    (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x760) /* linkdown_clr_port_en */

/* HIPCIEC50_DL_REG Base address of Module's Register */
#define CSR_HIPCIEC50_DL_REG_BASE (0x60000)

/* **************************************************************************** */
/*                      HIPCIEC50_DL_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_DL_REG_TX_FC_INIT_CYCLE_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x0) /* the initial fc DLLP frequency \
                                                                                     */
#define CSR_HIPCIEC50_DL_REG_FC_INIT_TIMEOUT_LIMIT_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x4) /* the limit value of initial FC in all time */
#define CSR_HIPCIEC50_DL_REG_VC_FC_INIT_ALLTIMEOUT_HANDING_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x8) /* the VC initializtion timeout handing */
#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_G1_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0xC) /* the ack transmission latency limit for 2.5GT/s mode */
#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_G2_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x10) /* the ack transmission latency limit for 5GT/s mode */
#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_G3_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x14) /* the ack transmission latency limit for 8GT/s mod */
#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_G4_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x18) /* the ack transmission latency limit for 16GT/s mod */
#define CSR_HIPCIEC50_DL_REG_ACK_NAKD_TLP_NUM_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x1C) /* the limit value of received number of not acknowledged TLP. */
#define CSR_HIPCIEC50_DL_REG_DFX_DUP_ACK_NUM_LIMIT_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x20) /* duplicate TLP received num limit. */
#define CSR_HIPCIEC50_DL_REG_DFX_NAK_TIME_LIMIT_REG \
    (CSR_HIPCIEC50_DL_REG_BASE +                    \
        0x24) /* the limit value between transimitted a NAK DLLP to received the last ACK DLLP. */
#define CSR_HIPCIEC50_DL_REG_CREDIT_NULL_FOR_SET_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x28) /* set credit null enable,count timer limit value. */
#define CSR_HIPCIEC50_DL_REG_REPLAY_CYCLE_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x2C) /* the replay time cycle for all mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_G1_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x30) /* the update timer for 2.5GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_G2_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x34) /* the update timer for 5GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_G3_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x38) /* the update timer for 8GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_G4_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x3C) /* the update timer for 16GT/s mode */
#define CSR_HIPCIEC50_DL_REG_RX_FC_UPDATE_TIME_LIMIT_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x40) /* update DLLP timeout error vaules */
#define CSR_HIPCIEC50_DL_REG_ECC_ERR_CNT_1BIT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x44)       /* ECC error occur count */
#define CSR_HIPCIEC50_DL_REG_ECC_ERR_CNT_2BIT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x48)       /* ECC error occur count */
#define CSR_HIPCIEC50_DL_REG_DATA_RAM0_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x4C) /* ECC error address */
#define CSR_HIPCIEC50_DL_REG_DFX_LCRC_ERR_NUM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x50)       /* the lcrc error number */
#define CSR_HIPCIEC50_DL_REG_DFX_DCRC_ERR_NUM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x54) /* the crc error clear signal */
#define CSR_HIPCIEC50_DL_REG_DFX_FSM_STATE_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x58)    /* DFX signal of FSM state */
#define CSR_HIPCIEC50_DL_REG_DFX_RETRY_STR_SEQ_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x5C) /* DFX the Seq_Num of start retry TLP */
#define CSR_HIPCIEC50_DL_REG_DFX_RETRY_STATUS_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x60) /* DFX signal of retry buffer read/write pointer */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_CTRL_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x64) /* apb read retry buffer address & start signal */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA0_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x68) /* apb read retry bufferdata DW0 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA1_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x6C) /* apb read retry bufferdata DW1 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA2_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x70) /* apb read retry bufferdata DW2 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA3_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x74) /* apb read retry bufferdata DW3 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA4_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x78) /* apb read retry bufferdata DW4 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA5_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x7C) /* apb read retry bufferdata DW5 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA6_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x80) /* apb read retry bufferdata DW6 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA7_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x84)                                            /* apb read retry bufferdata DW7 */
#define CSR_HIPCIEC50_DL_REG_DL_INT_STATUS_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x88) /* data link original intrrrupt */
#define CSR_HIPCIEC50_DL_REG_DL_INT_MASK_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x8C)   /* data link intrrrupt mask reg */
#define CSR_HIPCIEC50_DL_REG_DL_INT_RO_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x90) /* DL block common interrupt after mask \
                                                                               */
#define CSR_HIPCIEC50_DL_REG_DL_INT_SET_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x94) /* DL block common interrupt config by CPU */
#define CSR_HIPCIEC50_DL_REG_INFINITE_CREDIT_EN_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x98) /* when the vc initial is infinite credit,whether send UpdateFC DLLP. */
#define CSR_HIPCIEC50_DL_REG_TX_VEDNDOR_DLLP_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x9C) /* whether send vendor DLLP */
#define CSR_HIPCIEC50_DL_REG_RX_VENDOR_DLLP_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xA0)
#define CSR_HIPCIEC50_DL_REG_SRAM_ECC_CFG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xA4) /* sram ecc configuration */
#define CSR_HIPCIEC50_DL_REG_DFX_APB_READ_RETRY_DONE_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0xA8) /* dl_dfx_apb_read_retry_done */
#define CSR_HIPCIEC50_DL_REG_DFX_UPDATE_TIME_CYCLE_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0xAC) /* dfx for update long req not gnt */
#define CSR_HIPCIEC50_DL_REG_DFX_CRC_INSERT_ERROR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xB0) /* insert crc error for tx */
#define CSR_HIPCIEC50_DL_REG_DFX_MAC_BP_TIMER_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0xB4) /* how long for mac give rdy when vld is high */
#define CSR_HIPCIEC50_DL_REG_DFX_RETRY_CNT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xB8)         /* count retry timer */
#define CSR_HIPCIEC50_DL_REG_FC_PH_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xBC)      /* ph credit increasegap */
#define CSR_HIPCIEC50_DL_REG_FC_PD_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xC0)      /* pd credit increasegap */
#define CSR_HIPCIEC50_DL_REG_FC_NPH_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xC4)     /* nph credit increasegap */
#define CSR_HIPCIEC50_DL_REG_FC_NPD_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xC8)     /* npd credit increasegap */
#define CSR_HIPCIEC50_DL_REG_FC_CPLH_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xCC)    /* cplh credit increasegap */
#define CSR_HIPCIEC50_DL_REG_FC_CPLD_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xD0)    /* cpld credit increasegap */
#define CSR_HIPCIEC50_DL_REG_DL_MAC_RETRAIN_CNT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xD4)    /* count retrain */
#define CSR_HIPCIEC50_DL_REG_DL_MAC_RETRAIN_LIMIT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xD8)  /* retrain limit */
#define CSR_HIPCIEC50_DL_REG_INIT_FC_SEND_EN_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xDC)       /* init fc send enable */
#define CSR_HIPCIEC50_DL_REG_DFX_DLLP_RX_COUNT_NUM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xE0) /* count rx dllp number */
#define CSR_HIPCIEC50_DL_REG_DFX_DLLP_TX_COUNT_NUM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xE4) /* count tx dllp number */
#define CSR_HIPCIEC50_DL_REG_DFX_SEND_EN_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xE8)           /* tx send enable */
#define CSR_HIPCIEC50_DL_REG_DFX_SEQ_NUM_CHANGE_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0xEC)                                               /* is may change seqence number */
#define CSR_HIPCIEC50_DL_REG_DFX_DLLP_TYPE_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xF0)    /* config dllp type */
#define CSR_HIPCIEC50_DL_REG_DFX_RX_UPDATE_EN_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xF4) /* rx update dllp enable */
#define CSR_HIPCIEC50_DL_REG_DFX_RX_NAK_COUNT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xF8) /* count rx nak number */
#define CSR_HIPCIEC50_DL_REG_DFX_RX_BAD_DLLP_TYPE_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xFC) /* bad dllp type indicate */
#define CSR_HIPCIEC50_DL_REG_DFX_ACKD_SEQ_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x100)        /* indicate ackd_seq */
#define CSR_HIPCIEC50_DL_REG_DFX_NEXT_TRANSMIT_SEQ_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x104)                                               /* indicate next_transmit_seq */
#define CSR_HIPCIEC50_DL_REG_DFX_NEXT_RCV_SEQ_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x108) /* indicate next_rcv_seq */
#define CSR_HIPCIEC50_DL_REG_ECO_DL_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x118)           /* add eco register */
#define CSR_HIPCIEC50_DL_REG_TX_FEATURE_TIMER_CFG_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x11C) /* send feature dllp timeout */
#define CSR_HIPCIEC50_DL_REG_DL_CORRECT_ERR_CNT_CFG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x120) /* correct error count */
#define CSR_HIPCIEC50_DL_REG_DL_FC_UPDATE_MODE_SEL_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x124)  /* dl_fc_update_mode_sel */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_G1_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x128) /* the update timer for 2.5GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_G2_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x12C) /* the update timer for 5GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_G3_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x130) /* the update timer for 8GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_G4_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x134) /* the update timer for 16GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_G1_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x138) /* the update timer for 2.5GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_G2_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x13C) /* the update timer for 5GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_G3_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x140) /* the update timer for 8GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_G4_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x144) /* the update timer for 16GT/s mode */
#define CSR_HIPCIEC50_DL_REG_DL_INT_CE_NFE_SEL_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x148) /* Select the CE or NFE Type for Interrupt */
#define CSR_HIPCIEC50_DL_REG_DL_NI_INT_RO_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x14C) /* The normal interrupt status for DL */
#define CSR_HIPCIEC50_DL_REG_DL_FE_INT_RO_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x150) /* The fatal Error interrupt status for DL */
#define CSR_HIPCIEC50_DL_REG_DL_CE_INT_RO_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x154) /* The correctable Error  interrupt status for DL */
#define CSR_HIPCIEC50_DL_REG_DL_NFE_INT_RO_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x158) /* The nonfatal Error  interrupt status for DL */
#define CSR_HIPCIEC50_DL_REG_DL_FC_INIT_ERR_STATUS_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x15C) /* data link layer fc init timeout err status */
#define CSR_HIPCIEC50_DL_REG_DFX_RETRY_DATA_BUFFER_STATUS_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x160) /* DFX signal of retry buffer read/write pointer */
#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_G5_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x164) /* the ack transmission latency limit for 32GT/s mod */
#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_20G_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x168) /* the ack transmission latency limit for 20GT/s mod */
#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_25G_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x16C) /* the ack transmission latency limit for 25GT/s mod */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_G5_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x170) /* the update timer for 32GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_20G_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x174) /* the update timer for 20GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_25G_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x178) /* the update timer for 25GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_G5_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x17C) /* the update timer for 32GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_20G_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x180) /* the update timer for 20GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_25G_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x184) /* the update timer for 25GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_G5_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x188) /* the update timer for 32GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_20G_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x18C) /* the update timer for 20GT/s mode */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_25G_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x190)                                         /* the update timer for 25GT/s mode */
#define CSR_HIPCIEC50_DL_REG_DFX_DLCMSM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x194) /* dlcmsm dfx register */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA8_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x19C) /* apb read retry bufferdata DW8 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA9_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x200) /* apb read retry bufferdata DW9 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA10_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x204) /* apb read retry bufferdata DW10 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA11_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x208) /* apb read retry bufferdata DW11 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA12_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x20C) /* apb read retry bufferdata DW12 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA13_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x210) /* apb read retry bufferdata DW13 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA14_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x214) /* apb read retry bufferdata DW14 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA15_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x218) /* apb read retry bufferdata DW15 */
#define CSR_HIPCIEC50_DL_REG_DFX_APB_READ_CONTEXT_DONE_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x21C) /* dl_dfx_apb_read_context_done */
#define CSR_HIPCIEC50_DL_REG_APB_READ_CONTEXT_CTRL_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x220) /* apb read context buffer address & start signal */
#define CSR_HIPCIEC50_DL_REG_APB_READ_CONTEXT_DATA0_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x224) /* apb read context buffer data DW0 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_CONTEXT_DATA1_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x228) /* apb read context buffer data DW1 */
#define CSR_HIPCIEC50_DL_REG_APB_READ_CONTEXT_DATA2_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x22C) /* apb read context buffer data DW2 */
#define CSR_HIPCIEC50_DL_REG_CONTEXT_SRAM_ECC_CFG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x230)   /* sram ecc configuration */
#define CSR_HIPCIEC50_DL_REG_DATA_RAM1_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x234) /* ECC error address */
#define CSR_HIPCIEC50_DL_REG_DATA_RAM2_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x238) /* ECC error address */
#define CSR_HIPCIEC50_DL_REG_DATA_RAM3_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x23C) /* ECC error address */
#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM_ECC_ERR_CNT_1BIT_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x240) /* ECC error occur count */
#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM_ECC_ERR_CNT_2BIT_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x244) /* ECC error occur count */
#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM0_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x248) /* ECC error address */
#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM1_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x24C) /* ECC error address */
#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM2_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x250) /* ECC error address */
#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM3_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x254) /* ECC error address */
#define CSR_HIPCIEC50_DL_REG_RAM_ECC_ERR_INT_SEL_IND_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x258)   /* ecc error ram select \
                                                                                                */
#define CSR_HIPCIEC50_DL_REG_INSERT_IDLE_FSM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x25C) /* insert idle fsm state */
#define CSR_HIPCIEC50_DL_REG_DFX_MAC_ERR_NUM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x260) /* the mac2dl error number */
#define CSR_HIPCIEC50_DL_REG_RETRY_BUFFER_WATERLINE_X1_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x264) /* retry buffer full waterline control */
#define CSR_HIPCIEC50_DL_REG_RETRY_BUFFER_WATERLINE_X2_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x268) /* retry buffer full waterline control */
#define CSR_HIPCIEC50_DL_REG_RETRY_BUFFER_WATERLINE_X4_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x26C) /* retry buffer full waterline control */
#define CSR_HIPCIEC50_DL_REG_RETRY_BUFFER_WATERLINE_X8_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x270) /* retry buffer full waterline control */
#define CSR_HIPCIEC50_DL_REG_RETRY_BUFFER_WATERLINE_X16_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x274) /* retry buffer full waterline control */
#define CSR_HIPCIEC50_DL_REG_DFX_ACK_FFFH_INITAL_MASK_DISABLE_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x278)                                           /* disable ack_fffh_inital_mask */
#define CSR_HIPCIEC50_DL_REG_DFX_TX_DLLPG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x27C) /* dfx for TX_DLLPG */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_IDLE_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x280) /* tx fc update p cycle idle */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_IDLE_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x284) /* tx fc update np cycle idle */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_IDLE_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x288) /* tx fc update cpl cycle idle */
#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CYCLE_ALL_IDLE_EN_REG \
    (CSR_HIPCIEC50_DL_REG_BASE + 0x28C) /* tx fc update cycle all idle en */

/* HIPCIEC50_MAC_REG Base address of Module's Register */
#define CSR_HIPCIEC50_MAC_REG_BASE (0x70000)

/* **************************************************************************** */
/*                      HIPCIEC50_MAC_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_MAC_REG_MAC_REQ_EIOS_TO_ELEIDLE_DELAY_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x0) /* Receive EIOS to phy_eleidle delay */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ENTER_LOOPBACK_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4) /* LTSSM enter loopback mode enable */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RETRAIN_LINK_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x8) /* retrain link enable */
#define CSR_HIPCIEC50_MAC_REG_MAC_REQ_TX_LINK_NUM_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0xC) /* setting TX Link number advertising to Link parter when being as DS port. */
#define CSR_HIPCIEC50_MAC_REG_MAC_REQ_SCRAMBLE_DISABLE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x10) /* scramble disable */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SKP_INTVAL_SRIS_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x14) /* SKP interval in SRIS mode */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DC_BALANCE_DISABLE_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x18) /* DC balance funciton disanle */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_DISABLE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x1C) /* TX EQ function disable */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SUPPORTED_TX_PRESET_BM_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x20) /* TX EQ supported tx preset bit map */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_8G_PHY_EQ_FB_SEL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x24) /* PHY 8G TX EQ feedback mode sel */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN3_TX_COEFF_MAP_MODE_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x28) /* TX coeff mapping mode */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_PHASE23_CONV_STEP_ADDR_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE +                                   \
        0x2C) /* TX EQ convergence steps reqired when in TX_EQ2 (US port) or TX_EQ3 (DS port) */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_PHASE23_TIMEOUT_VAL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x30) /* TX EQ timeout value for TX_EQ phase2 and phase3, unit (ms) */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SKP_INTVAL_SRNS_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x34) /* SKP interval in SRNS mode */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_N_FTS_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x38) /* number of FTS need to be transmit during L0s back to L0 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PHYSTATUS_DET_TIMEOUT_VAL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3C) /* phystatus detection timeout value */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RDN_CROSS_TIMEOUT_VAL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x40) /* Random cross timeout value */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SEL_DEEMPH_US_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x44) /* sel_deemph for Upstream port */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_TX_COMP_RCV_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x48)                                               /* transmit complaince receive */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_TXSWING_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4C) /* Tx swing selection */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_INPUT_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x50)                                                      /* LTSSM tracer input */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_MAC_INT_STATUS_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x54) /* Interrupt status */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_MAC_INT_MASK_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x58)   /* interrupt mask */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_TEST_COUNTER_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x5C)   /* test counter set */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LINK_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x60)      /* mac link information */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x64)   /* debug PIPE signal set1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x68)   /* debug PIPE signal set2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x6C)   /* debug PIPE signal set3 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE4_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x70)   /* debug PIPE signal set4 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_RXDLI_1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x74) /* debug RXDLI signal */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LINK_NUM_1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x78) /* debug_link_num */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LANE_NUM_1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x7C) /* debug_lane_num */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_TXDLI_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x80)      /* debug TXDLI */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_OUTPUT_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x84) /* LTSSM tracer output */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_LAST_ADDR_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x88) /* LTSSM tracer last write address */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SYMBOL_UNLOCL_COUNTER_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x8C)                                                   /* symbol_unlock_counter */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_MAC_INT_RO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x90)  /* Interrupt status RO */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_MAC_INT_SET_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x94) /* interrupt sets */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ENTER_L1L2_TIMEOUT_VAL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x98) /* enter L1L2 state timeout */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_FIX_LP_TX_PRESET_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x9C) /* Tx EQ pahse fix link partner preset */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ADJ_HILINK_MODE_EN_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0xA0) /* adjust hilink SERDES function mode enable */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LP_GEN3_TX_PRESET_P1_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0xA4) /* tx preset value latched in GEN3 P1 state */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_OPT_TX_PRESET_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0xA8) /* TX EQ opimal TX PRESET result */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LOOPBACK_PRESET_TIMEOUT_VAL_ADDR_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0xAC) /* P2 or P3 wait for tx preset loopback timeout value */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_COMP_OPTION_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xB0)   /* Compliance option */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PHY_RXDATA_TS_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xB4) /* PIPE RX data */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ECO_RSV0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xB8)      /* ECO reserve register 0 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ECO_RSV1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xBC)      /* ECO reserve register 1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REGEQ_TRACE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xC0)       /* mac_eq_trace_reg */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_TIMEOUT_SET_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xC4)    /* mac_eq_timeout_reg */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_INIT_COEFF_CFG_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xC8) /* eq_init_coeff_cfg \
                                                                                                 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_WAIT_LINK_NUM_TIMER_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0xCC) /* mac_wait_link_num_timer */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x100) /* Lane0～lane7 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x104) /* Lane0～lane7 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x108) /* Lane0～lane7 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_3_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x10C) /* Lane0～lane7 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_4_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x110) /* Lane0～lane7 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_5_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x114) /* Lane0～lane7 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_6_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x118) /* Lane0～lane7 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_7_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x11C) /* Lane0～lane7 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x200)     /* Preset0 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x204)     /* Preset1 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x208)     /* Preset2 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x20C)     /* Preset3 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET4_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x210)     /* Preset4 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET5_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x214)     /* Preset5 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET6_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x218)     /* Preset6 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET7_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x21C)     /* Preset7 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET8_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x220)     /* Preset8 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET9_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x224)     /* Preset9 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET10_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x228)    /* Preset10 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET11_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x22C)    /* Preset11 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET12_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x230)    /* Preset12 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET13_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x234)    /* Preset13 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET14_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x238)    /* Preset14 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET15_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x23C)    /* Preset15 coeff for Lane */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE5_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x240) /* debug PIPE signal set5 \
                                                                                            */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE6_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x244) /* debug PIPE signal set6 \
                                                                                            */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE7_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x248) /* debug PIPE signal set7 \
                                                                                            */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE8_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x24C) /* debug PIPE signal set8 \
                                                                                            */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE9_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x250) /* debug PIPE signal set9 \
                                                                                            */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE10_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x254) /* debug PIPE signal set10 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE11_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x258) /* debug PIPE signal set11 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_RXDLI_2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x25C)    /* debug RXDLI signal */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LINK_NUM_2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x260) /* debug_link_num */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LINK_NUM_3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x264) /* debug_link_num */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LINK_NUM_4_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x268) /* debug_link_num */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LANE_NUM_2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x26C) /* debug_lane_num */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LANE_NUM_3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x270) /* debug_lane_num */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LANE_NUM_4_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x274) /* debug_lane_num */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LP_GEN3_TX_PRESET_P1_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x278) /* tx preset value latched in GEN3 P1 state */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN3_EQ_OPT_TX_PRESET_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x27C) /* TX EQ opimal TX PRESET result */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x280) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x284) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x288) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_3_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x28C) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_4_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x290) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_5_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x294) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_6_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x298) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_7_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x29C) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_OUTPUT_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2A0) /* LTSSM tracer output */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_OUTPUT_OK_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2A4) /* LTSSM tracer output */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_SRAM_ECC_INSERT_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2A8) /* LTSSM tracer output */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_ECC_ERR_ADDR_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2AC) /* LTSSM tracer output */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_COEFF_SEARCH_TRACER_OUTPUT_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2B0) /* COEFF_SEARCH tracer output */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_REMOTE_FS_LF_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2B4) /* REMOTE_PHY_FS_LF */
#define CSR_HIPCIEC50_MAC_REG_MAC_LOOP_LINK_DATA_ERR_COUNT_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2B8) /* loopback_link_data_err_count */
#define CSR_HIPCIEC50_MAC_REG_MAC_PCS_RX_ERR_CNT_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2BC) /* pcs_rx_err_cnt */
#define CSR_HIPCIEC50_MAC_REG_MAC_UP_MAX_AUTO_REDO_NUM_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2C0) /* up_max_auto_redo_number */
#define CSR_HIPCIEC50_MAC_REG_MAC_WAIT_LANE_NUM_TIMER_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2C4) /* mac_wait_lane_num_timer */
#define CSR_HIPCIEC50_MAC_REG_MAC_LANE_NUM_WAIT_TIMER_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2C8) /* mac_lane_num_wait_timer */
#define CSR_HIPCIEC50_MAC_REG_MAC_LANE_NUM_ACC_TIMER_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2CC) /* mac_lane_num_acc_timer */
#define CSR_HIPCIEC50_MAC_REG_MAC_LNW_TO_LNA_1MS_TIMER_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2D0) /* mac_lnw_to_lna_1ms_timer */
#define CSR_HIPCIEC50_MAC_REG_MAC_EQ_LTSMM_HOLD_TIMER_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2D4) /* mac_eq_ltssm_hold_timer */
#define CSR_HIPCIEC50_MAC_REG_MAC_LTSSM_CRTL_INFER_ELECIDLE_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2D8) /* mac_ltssm_ctrl_infer_elecidle */
#define CSR_HIPCIEC50_MAC_REG_MAC_LTSSM_TRACER_CFG0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2DC) /* mac_ltssm_tracer_cfg0 \
                                                                                              */
#define CSR_HIPCIEC50_MAC_REG_MAC_LTSSM_TRACER_CFG1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2E0) /* mac_ltssm_tracer_cfg1 \
                                                                                              */
#define CSR_HIPCIEC50_MAC_REG_MAC_CMP_LOOP_SENT_EQTS1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2E8) /* mac_cmp_loop_sent_eq_ts */
#define CSR_HIPCIEC50_MAC_REG_MAC_ENTER_LPBK_DISABLE_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2EC)                                                 /* mac_enter_lpbk_disable */
#define CSR_HIPCIEC50_MAC_REG_MAC_PRESET_TABLE0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2F0) /* mac_preset_table0 */
#define CSR_HIPCIEC50_MAC_REG_MAC_PRESET_TABLE1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2F4) /* mac_preset_table1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACERADDR_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2F8) /* LTSSM tracer addr \
                                                                                                 */
#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_COMPLETE_TIMER_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x2FC) /* maccfg_complete_timer */
#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_COMP_ERRATA_DISABLE_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x300)                                                   /* comp_errata_disable */
#define CSR_HIPCIEC50_MAC_REG_MAC_RX_ERR_CHECK_EN_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x304) /* mac_rx_error_check_en */
#define CSR_HIPCIEC50_MAC_REG_MAC_TRACE_2BIT_ECC_CNT_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x308) /* mac_ecc_2bit_er_cnt \
                                                                                               */
#define CSR_HIPCIEC50_MAC_REG_MAC_TRACE_1BIT_ECC_CNT_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x30C) /* mac_ecc_1bit_er_cnt \
                                                                                               */
#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_RCV_HOLD_EN_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x310)    /* mac_rcv_hold_en */
#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_RCV_LOCK_HOLD_TIME_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x314) /* mac_rcv_lock_hold_time */
#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_RCV_CFG_HOLD_TIME_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x318) /* mac_rcv_cfg_hold_time */
#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_RCV_IDLE_HOLD_TIME_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x31C) /* mac_rcv_idle_hold_time */
#define CSR_HIPCIEC50_MAC_REG_MAC_LTSSM_INT_STATUS_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x320) /* mac_ltssm_int_match_state */
#define CSR_HIPCIEC50_MAC_REG_MAC_DESKEW_SYMBOL_UNLOCK_RCV_MASK_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x324) /* mac_deskew_symbol_unlock_recovery_mask */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN4_EQ_OPT_TX_PRESET_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x328) /* TX GNE4 EQ opimal TX PRESET result */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN4_EQ_OPT_TX_PRESET_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x32C) /* TX GEN4 EQ opimal TX PRESET result */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LP_GEN4_TX_PRESET_P1_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x330) /* tx preset value latched in GEN4 P1 state */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LP_GEN4_TX_PRESET_P1_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x334) /* tx preset value latched in GEN4 P1 state */
#define CSR_HIPCIEC50_MAC_REG_MAC_LPBK_DATA_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x338) /* Tx data in loopback state */
#define CSR_HIPCIEC50_MAC_REG_MAC_RX_MARGIN_SELF_CTRL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x33C)                                                   /* mac_reg_margn_sel_ctrl */
#define CSR_HIPCIEC50_MAC_REG_MAC_RX_MARGIN_CFG_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x340)   /* mac_rx_margin_cfg */
#define CSR_HIPCIEC50_MAC_REG_GEN4_RX_MARGIN_CPA0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x344) /* gen4_rx_margin_cap0 */
#define CSR_HIPCIEC50_MAC_REG_GEN4_RX_MARGIN_CPA1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x348) /* gen4_rx_margin_cap1 */
#define CSR_HIPCIEC50_MAC_REG_GEN4_RX_MARGIN_RSV_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x34C)  /* resvered for rx margin */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN3_EQ_FIX_TX_PRESET_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x350) /* TX GNE3 EQ fix TX PRESET value1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN3_EQ_FIX_TX_PRESET_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x354) /* TX GNE3 EQ fix TX PRESETvalue2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN4_EQ_FIX_TX_PRESET_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x358) /* TX GNE4 EQ fix TX PRESET value1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN4_EQ_FIX_TX_PRESET_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x35C) /* TX GNE4 EQ fix TX PRESETvalue2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x360) /* MAC_REG_PHASE01_COARSETUNE_START_TM_VALUE */
#define CSR_HIPCIEC50_MAC_REG_MAC_LTSSM_TIMEOUT_ENABLE_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x364)                                                     /* LTSSM_TIMEOUT_ENABLE */
#define CSR_HIPCIEC50_MAC_REG_MAC_LOOPBACK_EC_VALUE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x368) /* MAC_LOOPBACK_EC_VALUE \
                                                                                              */
#define CSR_HIPCIEC50_MAC_REG_MAC_LANE_REVERSE_CFG_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x36C)  /* MAC_LANE_REVERSE_CFG */
#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_SRIS_EN_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x370)      /* MAC_PIPE_SRIS_EN_CFG */
#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_EBUF_MODE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x374)   /* MAC_PIPE_EBUF_MODE_CFG */
#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_SRIS_EN0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x378)    /* MAC_EBUF_DEPTH_CFG0 */
#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_SRIS_EN1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x37C)    /* MAC_EBUF_DEPTH_CFG1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_SRIS_EN2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x380)    /* MAC_EBUF_DEPTH_CFG2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_SRIS_EN3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x384)    /* MAC_EBUF_DEPTH_CFG3 */
#define CSR_HIPCIEC50_MAC_REG_MAC_FRAMING_ERR_CNT_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x39C)  /* MAC_FRAMING_ERR_CNT */
#define CSR_HIPCIEC50_MAC_REG_MAC_FRAMING_ERR_CTRL_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3A0) /* MAC_FRAMING_ERR_CTRL */
#define CSR_HIPCIEC50_MAC_REG_MAC_LINKDOWN_REQ_MASK_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3A4) /* MAC_LINKDOWN_REQ_MASK \
                                                                                              */
#define CSR_HIPCIEC50_MAC_REG_MAC_INT_TYPE_SEL_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3A8)      /* MAC_INT_TYPE_SEL */
#define CSR_HIPCIEC50_MAC_REG_MAC_REQ_COEFF_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3AC)    /* MAC_REQ_COEFF_INFO */
#define CSR_HIPCIEC50_MAC_REG_MAC_RX_COEFF_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3B0)     /* MAC_RX_COEFF_INFO */
#define CSR_HIPCIEC50_MAC_REG_MAC_LEAVE_L0_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3B4)     /* MAC_LEAVE_L0_INFO */
#define CSR_HIPCIEC50_MAC_REG_MAC_GEN4_LOW_SKP_CFG_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3B8)  /* MAC_GEN4_LOW_SKP_CFG */
#define CSR_HIPCIEC50_MAC_REG_DFX_APB_LANE_ERROR_STATUS_0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3BC) /* DFX_APB_LANE_ERROR_STATUS_0 */
#define CSR_HIPCIEC50_MAC_REG_DFX_APB_LANE_ERROR_STATUS_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3C0) /* DFX_APB_LANE_ERROR_STATUS_1 */
#define CSR_HIPCIEC50_MAC_REG_REG_FIX_LP_8G_TX_COEFF_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3C4) /* REG_FIX_LP_8G_TX_COEFF */
#define CSR_HIPCIEC50_MAC_REG_REG_FIX_LP_16G_TX_COEFF_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3C8) /* REG_FIX_LP_16G_TX_COEFF */
#define CSR_HIPCIEC50_MAC_REG_REG_RXIDLE_DELAY_TIME_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3CC) /* REG_RXIDLE_DELAY_TIME \
                                                                                              */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_16G_PHY_EQ_FB_SEL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3D0) /* PHY 16G TX EQ feedback mode sel */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_TX_MARGIN_CTRL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3D4) /* mac_reg_tx_margin_ctrl */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_8GT_EQTS2_PRESET_0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3D8) /* TX PRESET value in UP 8GT EQ TS2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_8GT_EQTS2_PRESET_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3DC) /* TX PRESET value in UP 8GT EQ TS2 */
#define CSR_HIPCIEC50_MAC_REG_REG_RXVALID_DELAY_TIME_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3E0) /* REG_RXVALID_DELAY_TIME */
#define CSR_HIPCIEC50_MAC_REG_MAC_INT_CE_NFE_SEL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3E4) /* Select the CE or NFE Type for Interrupt */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_NI_INT_RO_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3E8) /* The normal interrupt status for MAC */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FE_INT_RO_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3EC) /* The fatal Error interrupt status for MAC */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_CE_INT_RO_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3F0) /* The correctable Error  interrupt status for MAC */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_NFE_INT_RO_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3F4) /* The nonfatal Error  interrupt status for MAC */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_16G_EQTS2_PRESET_0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x3FC) /* TX PRESET value in UP 16GT EQ TS2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_16G_EQTS2_PRESET_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x400) /* TX PRESET value in UP 16GT EQ TS2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_ESM_20G_EQTS2_PRESET0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x404) /* TX PRESET value in UP ESM_20GT EQ TS2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_ESM_20G_EQTS2_PRESET1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x408) /* TX PRESET value in UP USM_20GT EQ TS2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_ESM_25G_EQTS2_PRESET0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x40C) /* TX PRESET value in UP USM_25GT EQ TS2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_ESM_25G_EQTS2_PRESET1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x410) /* TX PRESET value in UP USM_25GT EQ TS2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_ESM_20G_TX_PRESET_VALUE0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x414) /* TX ESM_20G EQ fix TX PRESET value1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_ESM_20G_TX_PRESET_VALUE1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x418) /* TX ESM_20G EQ fix TX PRESET value2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_ESM_25G_TX_PRESET_VALUE0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x41C) /* TX ESM_25G EQ fix TX PRESET value1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_ESM_25G_TX_PRESET_VALUE1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x420) /* TX ESM_25G EQ fix TX PRESET value2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_32G_TX_PRESET_VALUE0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x424) /* TX 32G EQ fix TX PRESET value1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_32G_TX_PRESET_VALUE1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x428) /* TX 32G EQ fix TX PRESET value2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_56G_TX_PRESET_VALUE0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x42C) /* TX 56G EQ fix TX PRESET value1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_56G_TX_PRESET_VALUE1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x430) /* TX 56G EQ fix TX PRESET value2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_64G_TX_PRESET_VALUE0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x434) /* TX 64G EQ fix TX PRESET value1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_64G_TX_PRESET_VALUE1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x438) /* TX 64G EQ fix TX PRESET value2 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SKP_INTVL_GEN5_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x43C) /* GEN5 SKP interval in SRNS and SRIS mode */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SKP_INTVL_GEN6_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x440) /* GEN6 SKP interval in SRNS and SRIS mode */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SKP_INTVL_GEN7_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x444) /* GEN7 SKP interval in SRNS and SRIS mode */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_20G_EQ_FIX_LP_TX_COEFF_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x448) /* REG_FIX_LP_ESM_20G_TX_COEFF */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_25G_EQ_FIX_LP_TX_COEFF_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x44C) /* REG_FIX_LP_ESM_25G_TX_COEFF */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_32G_EQFIX_LP_TX_COEFF_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x450) /* REG_FIX_LP_32G_TX_COEFF */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_56G_EQ_FIX_LP_TX_COEFF_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x454) /* REG_FIX_LP_56G_TX_COEFF */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_64G_EQ_FIX_LP_TX_COEFF_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x458) /* REG_FIX_LP_64G_TX_COEFF */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_20G_LINK_EQ_CTRL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x45C) /* MAC REG LINK EQ CTRL in ESM_20GT/s */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_25G_LINK_EQ_CTRL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x460) /* MAC REG LINK EQ CTRL in ESM_25GT/s */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_32G_LINK_EQ_CTRL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x464) /* MAC REG LINK EQ CTRL in 32GT/s */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_56G_LINK_EQ_CTRL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x468) /* MAC REG LINK EQ CTRL in 56GT/s */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_64G_LINK_EQ_CTRL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x46C) /* MAC REG LINK EQ CTRL in 64GT/s */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_20G_EQ_FIX_LP_TX_PRESET_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x470) /* Tx EQ pahse fix link partner preset */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_25G_EQ_FIX_LP_TX_PRESET_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x474) /* Tx EQ pahse fix link partner preset */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_32G_EQ_FIX_LP_TX_PRESET_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x478) /* Tx EQ pahse fix link partner preset */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_56G_EQ_FIX_LP_TX_PRESET_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x47C) /* Tx EQ pahse fix link partner preset */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_64G_EQ_FIX_LP_TX_PRESET_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x480) /* Tx EQ pahse fix link partner preset */
#define CSR_HIPCIEC50_MAC_REG_MAC_LP_ESM_20G_TX_PRESET_P1_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x484) /* tx preset value latched in ESM_20G P1 state */
#define CSR_HIPCIEC50_MAC_REG_MAC_LP_ESM_20G_TX_PRESET_P1_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x488) /* tx preset value latched in ESM_20G P1 state */
#define CSR_HIPCIEC50_MAC_REG_MAC_LP_ESM_25G_TX_PRESET_P1_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x48C) /* tx preset value latched in ESM_25G P1 state */
#define CSR_HIPCIEC50_MAC_REG_MAC_LP_ESM_25G_TX_PRESET_P1_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x490) /* tx preset value latched in ESM_25G P1 state */
#define CSR_HIPCIEC50_MAC_REG_MAC_LP_GEN5_TX_PRESET_P1_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x494) /* tx preset value latched in GEN5 P1 state */
#define CSR_HIPCIEC50_MAC_REG_MAC_LP_GEN5_TX_PRESET_P1_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x498) /* tx preset value latched in GEN5 P1 state */
#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_ESM_20G_PRESET_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4A4) /* TX EQ opimal TX PRESET result */
#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_ESM_20G_PRESET_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4A8) /* TX EQ opimal TX PRESET result */
#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_ESM_25G_PRESET_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4AC) /* TX EQ opimal TX PRESET result */
#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_ESM_25G_PRESET_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4B0) /* TX EQ opimal TX PRESET result */
#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_GEN5_PRESET_1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4B4) /* TX EQ opimal TX PRESET result */
#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_GEN5_PRESET_2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4B8) /* TX EQ opimal TX PRESET result */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_DFX_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4D0) /* LTSSM DFX */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ALTERNATE_PROTOL_VENDER_ID_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4D4) /* VENDER ID FOR ALTERNATE_PROTOL */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_TS_MESSAGE_VENDER_ID_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4D8) /* VENDER ID FOR TS_MESSAGE */
#define CSR_HIPCIEC50_MAC_REG_MAC_HILINK_INFO_DFX_1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4DC)
#define CSR_HIPCIEC50_MAC_REG_MAC_HILINK_INFO_DFX_2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4E0)
#define CSR_HIPCIEC50_MAC_REG_MAC_HILINK_INFO_DFX_3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4E4)
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PLL_CTRL_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4E8) /* MAC PLL CTRL */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_USE_FIX_CORE_CLK_EN_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4EC) /* MAC CORE CLK SELECT FROM PLL OR HILINK MCLK32B */
#define CSR_HIPCIEC50_MAC_REG_MAC_EBUFFER_UPDATE_FREQUENCY0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4F8) /* EBUFFER_UPDATE_FREQUENCY FOR LANE0~LANE3 */
#define CSR_HIPCIEC50_MAC_REG_MAC_EBUFFER_UPDATE_FREQUENCY1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x4FC) /* EBUFFER_UPDATE_FREQUENCY FOR LANE4~LANE7 */
#define CSR_HIPCIEC50_MAC_REG_MAC_EBUFFER_UPDATE_FREQUENCY2_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x500) /* EBUFFER_UPDATE_FREQUENCY FOR LANE8~LANE11 */
#define CSR_HIPCIEC50_MAC_REG_MAC_EBUFFER_UPDATE_FREQUENCY3_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x504) /* EBUFFER_UPDATE_FREQUENCY FOR LANE12~LANE15 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PIPE_MODE_SEL_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x508) /* PIPE MODE SEL MESSAGEBUS OR PIN */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RPT_MBUS_DFX_LANE_ID_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x50C)                                                     /* RPT MBUS DFX LANE ID */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RPT_MBUS_DFX0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x510) /* MBUS DFX0 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RPT_MBUS_DFX1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x514) /* MBUS DFX1 */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RPT_MBUS_ERR_CNT_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x518) /* MBUS ERR CNT */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LCFSLF_USE_TXSTATUS_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x51C) /* LOCAL FS/LF USE TXSTATUS OR RXSTATUS */
#define CSR_HIPCIEC50_MAC_REG_MAC_PRECODING_CTRL_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x520)
#define CSR_HIPCIEC50_MAC_REG_MAC_RX_TERMATION_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x524)
#define CSR_HIPCIEC50_MAC_REG_MAC_POWERDOWN_VALUE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x528)
#define CSR_HIPCIEC50_MAC_REG_MAC_CLK_SW_TM_VAL_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x52C)
#define CSR_HIPCIEC50_MAC_REG_MAC_TXELEIDLE_TM_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x530)
#define CSR_HIPCIEC50_MAC_REG_MAC_TARGET_LINK_WIDTH_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x534)
#define CSR_HIPCIEC50_MAC_REG_MAC_LPBK_WAIT_TIME_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x538)
#define CSR_HIPCIEC50_MAC_REG_MAC_LPBK_DFX_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x53C)
#define CSR_HIPCIEC50_MAC_REG_TX_DLI_DEBUG_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x540)
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DESKEW_UNLOCL_COUNTER_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x544) /* deskew_unlock_counter */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RX_TSBUF_RESET_COUNTER_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x548)                                                    /* rxts_buf_reset_counter */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x54C) /* ltssm_internal_value0 \
                                                                                             */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x550) /* ltssm_internal_value1 \
                                                                                             */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x554) /* ltssm_internal_value2 \
                                                                                             */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x558) /* ltssm_internal_value3 \
                                                                                             */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE4_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x55C) /* ltssm_internal_value4 \
                                                                                             */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE5_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x560) /* ltssm_internal_value5 \
                                                                                             */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE6_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x564) /* ltssm_internal_value6 \
                                                                                             */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE7_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x568) /* ltssm_internal_value7 \
                                                                                             */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE8_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x56C) /* ltssm_internal_value8 \
                                                                                             */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE9_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x570) /* ltssm_internal_value9 \
                                                                                             */
#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE10_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x574) /* ltssm_internal_value10 */
#define CSR_HIPCIEC50_MAC_REG_MAC_P10_COEFF_HALF_RATE_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x578) /* mac_p10_coeff_half_rate */
#define CSR_HIPCIEC50_MAC_REG_MAC_RCV_EIOS_TO_ELEIDLE_DLY_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x57C) /* mac_rcv_eios_to_eleidle_delay */
#define CSR_HIPCIEC50_MAC_REG_GEN5_PHY_CAP_REG0_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x580) /* Gen5 Transmitted modify TS Data1 register */
#define CSR_HIPCIEC50_MAC_REG_GEN5_PHY_CAP_REG1_REG \
    (CSR_HIPCIEC50_MAC_REG_BASE + 0x584) /* Gen5 Transmitted modify TS Data2 register */
#define CSR_HIPCIEC50_MAC_REG_MAC_COEFF_TRACER_CFG1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x588) /* mac_coeff_tracer_cfg1 \
                                                                                              */

/* HIPCIEC50_TL_REG Base address of Module's Register */
#define CSR_HIPCIEC50_TL_REG_BASE (0x20000)

/* **************************************************************************** */
/*                      HIPCIEC50_TL_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_TL_REG_TL_TX_CTRL_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x0) /* Transaction Layer transmission control */
#define CSR_HIPCIEC50_TL_REG_TL_ENGIEN_STATUS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x4) /* tl tx status registers */
#define CSR_HIPCIEC50_TL_REG_TL_RX_CHECK_EN_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x8)                                          /* Error detct optional checker enable */
#define CSR_HIPCIEC50_TL_REG_LTR_REQUIRE_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xC) /* device LTR require */
#define CSR_HIPCIEC50_TL_REG_LTR_MSG_CTRL_STATUS_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x10) /* LTR message transmit control and status */
#define CSR_HIPCIEC50_TL_REG_TX_CRD_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x14)     /* TL_TX credit control signals */
#define CSR_HIPCIEC50_TL_REG_PM_NPD_CDT_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x1C) /* PM NPD credit  control */
#define CSR_HIPCIEC50_TL_REG_TL_TX_WRR_WEIGHT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x24) /* TL_TX P/NP/CPL transmission weight in WRR arbiter */
#define CSR_HIPCIEC50_TL_REG_TL_PORT_IDLE_CTRL_STATUS_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x28) /* TL port idle control and staus */
#define CSR_HIPCIEC50_TL_REG_TL_CFG_ACCESS_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xFC) /* Cfgspace APB access ctrl \
                                                                                        */
#define CSR_HIPCIEC50_TL_REG_TL_ASPM_IDLE_CNT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x100) /* ASPM self-launch control register */
#define CSR_HIPCIEC50_TL_REG_TL_ASPM_IDLE_EN_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x104) /* ASPM self-launch control register */
#define CSR_HIPCIEC50_TL_REG_TL_PM_DC_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x108) /* Power management DC control */
#define CSR_HIPCIEC50_TL_REG_TL_PM_STATE_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x10C)   /* Power management state */
#define CSR_HIPCIEC50_TL_REG_TL_PM_UC_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x114) /* Power management RX control */
#define CSR_HIPCIEC50_TL_REG_TL_ENTER_L0_CTRL_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x118) /* Power management wake up control */
#define CSR_HIPCIEC50_TL_REG_TL_PM_TIMEOUT_CTRL_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x11C) /* Power management timeout control */
#define CSR_HIPCIEC50_TL_REG_TL_PM_L1SUBSTATE_CTRL_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x120) /* PM L1 substate control registers */
#define CSR_HIPCIEC50_TL_REG_TL_PM_L1SUBSTATE_TIME_CFG0_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x124) /* The TIMEOUT VALUE configuration of L1 substate */
#define CSR_HIPCIEC50_TL_REG_TL_PM_L1SUBSTATE_TIME_CFG1_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x128)                                                  /* DFE timeout value of PM */
#define CSR_HIPCIEC50_TL_REG_TL_RX_ODR_CTRL_MODE_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x200) /* TL_RX ODR_CTRL_MODE */
#define CSR_HIPCIEC50_TL_REG_TL_RX_PFX_FILTER_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x210) /* Filter prefix in error detect */
#define CSR_HIPCIEC50_TL_REG_SYSTEM_ERR_OVERRIDE_CONTROL_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x4E4) /* SYSTEM ERROR CONTROL REGISTER FOR ROOT PORT */
#define CSR_HIPCIEC50_TL_REG_TL_CFG_HCK_EN_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x4E8) /* Control the RW/RO attributes of HCK warning register */
#define CSR_HIPCIEC50_TL_REG_TL_INT_STATUS0_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x56C) /* TL interrupt status0 */
#define CSR_HIPCIEC50_TL_REG_TL_INT_STATUS1_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x570) /* TL interrupt status1 */
#define CSR_HIPCIEC50_TL_REG_TL_INT_MASK0_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x574) /* transaction layer tx interrupt mask */
#define CSR_HIPCIEC50_TL_REG_TL_INT_SET0_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x578) /* transaction layer tx interrupt set register */
#define CSR_HIPCIEC50_TL_REG_TL_INT_RO0_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x57C) /* transaction layer tx interrupt indicater status */
#define CSR_HIPCIEC50_TL_REG_TL_INT_MASK1_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x580) /* transaction layer tx interrupt mask */
#define CSR_HIPCIEC50_TL_REG_TL_INT_SET1_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x584) /* transaction layer tx interrupt set register */
#define CSR_HIPCIEC50_TL_REG_TL_INT_RO1_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0x588) /* transaction layer tx interrupt indicater status */
#define CSR_HIPCIEC50_TL_REG_TL_INT_SEL0_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x590)        /* CE and NFE select signal */
#define CSR_HIPCIEC50_TL_REG_TL_INT_CE_RO_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x594)       /* CE interrupt status */
#define CSR_HIPCIEC50_TL_REG_TL_INT_NFE_RO_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x598)      /* NFE interrupt status */
#define CSR_HIPCIEC50_TL_REG_TL_INT_FE_RO_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x59C)       /* FE interrupt status */
#define CSR_HIPCIEC50_TL_REG_TL_TX_DFX_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xA00)     /* TL_TX DFX ontrol signals */
#define CSR_HIPCIEC50_TL_REG_TL_TX_SYNC_FIFO_ST_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xA04) /* TL TX SYNC FIFO Status */
#define CSR_HIPCIEC50_TL_REG_TL_TX_WHOLE_TLP_HED_VLD_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA08)                                           /* TL TX SYNC FIFO Status */
#define CSR_HIPCIEC50_TL_REG_TL_TX_UR_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xA0C) /* TL TX UR error counter */
#define CSR_HIPCIEC50_TL_REG_TL_TX_VC0_P_FC_LEFT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA10) /* VC0 P header  and data flow credit left valud */
#define CSR_HIPCIEC50_TL_REG_TL_TX_VC0_NP_FC_LEFT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA14) /* VC0 NP header  and data flow credit left valud */
#define CSR_HIPCIEC50_TL_REG_TL_TX_VC0_CPL_FC_LEFT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA18) /* VC0 CPL header  and data flow credit left valud */
#define CSR_HIPCIEC50_TL_REG_TL_TX_VC1_P_FC_LEFT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA1C) /* CCIX VC P header  and data flow credit left valud */
#define CSR_HIPCIEC50_TL_REG_TL_TX_TC_MAPERR_TC_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA20) /* when TC map VC is error, remembor the error TLP's TC. */
#define CSR_HIPCIEC50_TL_REG_TL_TX_VC_CC_SCAL_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA24) /* TL_TX flow control credit consume and scale */
#define CSR_HIPCIEC50_TL_REG_TL_TX_VC_INF_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA28) /* TL_TX flow control infinite credit indicator */
#define CSR_HIPCIEC50_TL_REG_TL_TX_ORDER_P_NUM_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA2C) /* TL_TX ordering P TLP range number and send number */
#define CSR_HIPCIEC50_TL_REG_TL_TX_ORDER_NP_CPL_NUM_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA30) /* TL_TX ordering NP or CPL TLP range number and P TLP send number */
#define CSR_HIPCIEC50_TL_REG_TL_TX_NP_CPL_CRD_USED_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA34) /* TL_TX CPL credit used counter */
#define CSR_HIPCIEC50_TL_REG_TL_TX_VC_LOC_CRD_LIMIT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA38) /* P/NP/CPL header and data local credit limit */
#define CSR_HIPCIEC50_TL_REG_TL_TX_VC_COM_CRD_CC_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA3C) /* P/NP/CPL header and data link and local credit consume */
#define CSR_HIPCIEC50_TL_REG_TL_TX_TAG_USED_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xA40) /* PORT tag used counter */
#define CSR_HIPCIEC50_TL_REG_TL_CFGSPACE_BDF_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA44) /* TL CFGSPACE BUS NUMBER AND DEVICE NUMBER */
#define CSR_HIPCIEC50_TL_REG_TL_TX_LTR_MSG_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xA48) /* TL TX UR error counter */
#define CSR_HIPCIEC50_TL_REG_TL_TX_SYNC_FIFO_OVERFLOW_STS_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xA4C) /* TLTX SYNC FIFO OVERFLOW */
#define CSR_HIPCIEC50_TL_REG_TL_RX_VC0_POST_CREDIT_LEFT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB00) /* VC0_POST_CREDIT */
#define CSR_HIPCIEC50_TL_REG_TL_RX_VC0_NONPOST_CREDIT_LEFT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB04)                                                        /* VC0_NONPOST_CREDIT */
#define CSR_HIPCIEC50_TL_REG_TL_RX_VC0_CPL_CREDIT_LEFT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB08) /* VC0_CPL_CREDIT */
#define CSR_HIPCIEC50_TL_REG_RX_RX_BUFFER_STATUS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB18) /* RX BUFFER FIFO STATUS */
#define CSR_HIPCIEC50_TL_REG_TL_RX_POSTED_CREDIT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB1C) /* TL RX CREDIT POSTED TLP INITIAL SIZE */
#define CSR_HIPCIEC50_TL_REG_TL_RX_NON_POSTED_CREDIT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB20) /* TL RX CREDIT NON_POSTED TLP INITIAL SIZE */
#define CSR_HIPCIEC50_TL_REG_TL_RX_CPL_CREDIT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB24) /* TL RX CREDIT CPL TLP INITIAL SIZE */
#define CSR_HIPCIEC50_TL_REG_TL_RX_CDT_INI_UP_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB28)                                            /* TL RX CREDIT reconfigure enable */
#define CSR_HIPCIEC50_TL_REG_TL_RX_ERR_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB2C) /* RX Error counter */
#define CSR_HIPCIEC50_TL_REG_TL_RX_NULL_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB30) /* RX null/dl Error counter */
#define CSR_HIPCIEC50_TL_REG_TL_RX_UR_TLP_CNT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB34)                                              /* RX received tlp is UR counter */
#define CSR_HIPCIEC50_TL_REG_TL_RX_TOTAL_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB38) /* RX received total tlp counter \
                                                                                      */
#define CSR_HIPCIEC50_TL_REG_TL_RX_TOTAL_TR_CNT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB3C)                                             /* RX total sending tlps counter */
#define CSR_HIPCIEC50_TL_REG_TL_RX_DROP_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB40) /* RX drop tlps counter */
#define CSR_HIPCIEC50_TL_REG_TL_RX_POST_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB44) /* RX post tlp counter */
#define CSR_HIPCIEC50_TL_REG_TL_RX_NONPOST_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB48) /* RX non-post tlp counter */
#define CSR_HIPCIEC50_TL_REG_TL_RX_CPL_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB4C)     /* RX completion tlp counter */
#define CSR_HIPCIEC50_TL_REG_TL_RX_LOC_TLP_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB50) /* RX Local hit TLP counter */
#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX0_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB58)   /* TL RX DFX 0 */
#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX1_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB5C)   /* TL RX DFX 1 */
#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX2_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB60)   /* TL RX DFX 2 */
#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX3_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB64)   /* TL RX DFX 3 */
#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX4_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB68)   /* TL RX DFX 4 */
#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX5_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB6C)   /* TL RX DFX 5 */
#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX6_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB70)   /* TL RX DFX 6 */
#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX7_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB74)   /* TL RX DFX 7 */
#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX8_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB78)   /* TL RX DFX 8 */
#define CSR_HIPCIEC50_TL_REG_TL_RX_POSTED_CREDIT_DF_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB88) /* TL RX CREDIT POSTED TLP INITIAL SIZE */
#define CSR_HIPCIEC50_TL_REG_TL_RX_NON_POSTED_CREDIT_DF_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB8C) /* TL RX CREDIT NON_POSTED TLP INITIAL SIZE */
#define CSR_HIPCIEC50_TL_REG_TL_RX_CPL_CREDIT_DF_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB90) /* TL RX CREDIT CPL TLP INITIAL SIZE */
#define CSR_HIPCIEC50_TL_REG_TL_RX_CDT_INI_UP_DF_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB94) /* TL RX CREDIT reconfigure enable */
#define CSR_HIPCIEC50_TL_REG_RX_ASYN_STONE_FIFO_STATUS_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xB98) /* The asyn and stone fifo of tl rx */
#define CSR_HIPCIEC50_TL_REG_TL_RX_ERR_STATUS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB9C)       /* TL RX ERROR STATUS */
#define CSR_HIPCIEC50_TL_REG_TL_RX_ECC_ERROR_STATUS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBA0) /* tl rx ecc error status \
                                                                                             */
#define CSR_HIPCIEC50_TL_REG_TL_RX_BP_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBA4) /* tl rx back preture signal */
#define CSR_HIPCIEC50_TL_REG_TL_RX_ECC_1BIT_ERR_CNT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBA8) /* TL RX 1bit ECC Error counter */
#define CSR_HIPCIEC50_TL_REG_TL_RX_ECC_1BIT_ERR_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBAC) /* TL ecc 1bit error report */
#define CSR_HIPCIEC50_TL_REG_TL_ECC_2BIT_ERR_CNT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBB0) /* RX buffer 2bit ECC Error counter */
#define CSR_HIPCIEC50_TL_REG_TL_ECC_2BIT_ERR_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBB4) /* tl rx buffer ecc 2bit error report */
#define CSR_HIPCIEC50_TL_REG_TL_RX_INSERT_ECC_ERR_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBB8) /* tl rx insert ECC error */
#define CSR_HIPCIEC50_TL_REG_TL_RX_POSTED_CREDIT_WATERLINE_CFG_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBBC) /* tl rx credit waterline configuration */
#define CSR_HIPCIEC50_TL_REG_TL_RX_NPOSTED_CREDIT_WATERLINE_CFG_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBC0) /* tl rx credit waterline configuration */
#define CSR_HIPCIEC50_TL_REG_TL_RX_CPL_CREDIT_WATERLINE_CFG_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBC4) /* tl rx credit waterline configuration */
#define CSR_HIPCIEC50_TL_REG_TL_PM_DL_L2_GNT_TIME_CFG_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBC8) /* The TIMEOUT VALUE configuration of L2 for dl response gnt */
#define CSR_HIPCIEC50_TL_REG_TL_PM_DL_L1_GNT_TIME_CFG_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBCC) /* The TIMEOUT VALUE configuration of L1 for dl response gnt */
#define CSR_HIPCIEC50_TL_REG_TL_PM_DL_L0S_GNT_TIME_CFG_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBD0) /* The TIMEOUT VALUE configuration of L0S for dl response gnt */
#define CSR_HIPCIEC50_TL_REG_TL_PM_L1SUBSTATE_REFCLK_STABEL_TIME_CFG_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBD4) /* The reclk stable TIME VALUE for L1 substate */
#define CSR_HIPCIEC50_TL_REG_PM_STATUS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBD8) /* power management dfx */
#define CSR_HIPCIEC50_TL_REG_TL_PM_LASTACK_TIME_CFG_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBDC) /* The TIMEOUT VALUE configuration for dl clean retry_buffer */
#define CSR_HIPCIEC50_TL_REG_TL_PM_LTR_LATTENCY_RCV_DFX_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBE0) /* the LTR latency VALUE received in RC mode for DFX */
#define CSR_HIPCIEC50_TL_REG_PM_STATUS_FIFO_CONTROL_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBE4)                                         /* the fifo control of pm state */
#define CSR_HIPCIEC50_TL_REG_PM_STATUS1_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBE8) /* power management dfx */
#define CSR_HIPCIEC50_TL_REG_PM_CLKCHANGE_REQ_TIME_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBEC) /* the time value that the pm2crg_clkchange_req must be stay in valid */
#define CSR_HIPCIEC50_TL_REG_PM_CLKCHANGE_GNT_TIME_REG                                                             \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBF0) /* the max time value that the clk  must be change from low freq to normal \
                                           freq after the negedge of pm2crg_clkchange_req */
#define CSR_HIPCIEC50_TL_REG_TL_PM_BLK_TLP_GNT_TIME_CFG_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBF4) /* The TIMEOUT VALUE configuration of blk tlp for tl response gnt */
#define CSR_HIPCIEC50_TL_REG_DOE_CAP_CRS_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBF8) /* DOE capability control status register */
#define CSR_HIPCIEC50_TL_REG_DOE_CAP_RD_DAT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xBFC) /* Local cpu read message from DOE capability */
#define CSR_HIPCIEC50_TL_REG_DOE_CAP_WR_DAT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xC00) /* Local cpu write response message into this register */
#define CSR_HIPCIEC50_TL_REG_TL_PM_L10_WAIT_ACK_TIMEOUT_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xC04) /* the timeout configuration of the pm state l10_wait_ack to l1n_wait_ack */
#define CSR_HIPCIEC50_TL_REG_TL_RX_TRACE_CMP_EN_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xC10) /* trace spcify info enable,and inbound or outbound select */
#define CSR_HIPCIEC50_TL_REG_TL_RX_REF_HEADER_DW0_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xC14) /* reference header DW0 for TL_RX trace. */
#define CSR_HIPCIEC50_TL_REG_TL_RX_REF_HEADER_DW1_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xC18) /* reference header DW1 for TL_RX trace. */
#define CSR_HIPCIEC50_TL_REG_TL_RX_REF_HEADER_DW2_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xC1C) /* reference header DW2 for TL_RX trace. */
#define CSR_HIPCIEC50_TL_REG_TL_RX_REF_HEADER_DW3_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xC20) /* reference header DW3 for TL_RX trace. */
#define CSR_HIPCIEC50_TL_REG_TL_RX_CAP_HEADER_DW0_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xC24) /* captured header DW0 for TL_RX trace. */
#define CSR_HIPCIEC50_TL_REG_TL_RX_CAP_HEADER_DW1_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xC28) /* captured header DW1 for TL_RX trace. */
#define CSR_HIPCIEC50_TL_REG_TL_RX_CAP_HEADER_DW2_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xC2C) /* captured header DW2 for TL_RX trace. */
#define CSR_HIPCIEC50_TL_REG_TL_RX_CAP_HEADER_DW3_REG \
    (CSR_HIPCIEC50_TL_REG_BASE + 0xC30) /* captured header DW3 for TL_RX trace. */
#define CSR_HIPCIEC50_TL_REG_TL_RX_TRACT_TLP_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xC34) /* CAPTURED TLP counter */
#define CSR_HIPCIEC50_TL_REG_TL_CFG_DOE_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xE00)      /* DOE cap counter */
#define CSR_HIPCIEC50_TL_REG_TL_CFG_DOE_STS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xE04)      /* DOE cap status */
#define CSR_HIPCIEC50_TL_REG_ECO_TL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xFFC) /* Add some registers for eco. */

/* HIPCIEC50_TL_CORE_REG Base address of Module's Register */
#define CSR_HIPCIEC50_TL_CORE_REG_BASE (0x30000)

/* **************************************************************************** */
/*                      HIPCIEC50_TL_CORE_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_TL_CORE_REG_APTL_ASYN_FIFO_CTRL_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x0) /* AP to TL asynchrous FIFO control */
#define CSR_HIPCIEC50_TL_CORE_REG_CORE_TL_TX_CTRL_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x4) /* Transaction Layer transmission control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_CHECK_CTRL_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x8) /* TL_TX completion context check control */
#define CSR_HIPCIEC50_TL_CORE_REG_TX_CRD_CTRL_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xC) /* TL_TX credit control signals */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_REG_CFG_ACCESS_CTRL_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x10) /* TL_REG_CFG_access ctrl signals */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_CTRL_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x20) /* Software postTLP generater */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_HEADER0_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x24) /* tlp header DW0 \
                                                                                                     */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_HEADER1_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x28) /* tlp header DW1 \
                                                                                                     */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_HEADER2_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x2C) /* tlp header DW2 \
                                                                                                     */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_HEADER3_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x30) /* tlp header DW3 \
                                                                                                     */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TLP_FUN_SEL_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x34) /* message function selection */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_DATA0_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x38) /* Payload DW 0 */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_DATA1_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x3C) /* Payload DW 1 */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_DATA2_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x40) /* Payload DW 2 */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_DATA3_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x44) /* Payload DW 3 */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_TIMER_CFG01_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x48) /* TL_TX completion timeout registers of default value. */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_TIMER_CFG23_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x4C) /* TL_TX completion timeout registers of default value. */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_TIMER_CFG45_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x50) /* TL_TX completion timeout registers of default value. */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_TIMER_CFG67_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x54) /* TL_TX completion timeout registers of default value. */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_TIMER_CFG8_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x58) /* TL_TX completion timeout registers of default value. */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_WAIT_IDLE_TIMER_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x100) /* TL wait idle timer configuration register. */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_PORT_IDLE_TOUT_TIMER_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x104) /* TL wait idle timer configuration register. */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_CDT_CFG_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x500) /* TL RX Credit (with AP/CPI) configuration */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_ATOMIC_DROP_CFG_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x504) /* TL atomic Drop configuration */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_MISC_CFG_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x508) /* TL RX MISC configuration */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_HIDX_FIFO_TH_VALUE_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x50C) /* TL RX HIDX FIFO threshold Value configuration */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_CPLH_FIFO_TH_VALUE_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x510) /* TL RX CPL FIFO threshold Value configuration */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_MSI_ADDR_WINDOW_L_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x514) /* TL RX MSI low 32 bit addr match window */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_MSI_ADDR_WINDOW_H_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x518) /* TL RX MSI high 32 bit addr match window */
#define CSR_HIPCIEC50_TL_CORE_REG_CFG_VPD_INT_STATUS_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x800) /* cfgspace VPD interrupt status */
#define CSR_HIPCIEC50_TL_CORE_REG_CFG_VPD_INT_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x804) /* cfgspace VPD interrupt  mask */
#define CSR_HIPCIEC50_TL_CORE_REG_CFG_VPD_INT_SET_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x808) /* cfgspace VPD interrupt  set register */
#define CSR_HIPCIEC50_TL_CORE_REG_CFG_VPD_INT_RO_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x80C) /* cfgspace VPD interrupt  RO status */
#define CSR_HIPCIEC50_TL_CORE_REG_CFG_FLR_INT_SEL_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x810) /* Where the FLR interrupt is report. To IEP or CORE interrupt line */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_INT_STATUS0_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x814) /* TL Core interrupt status */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_INT_MASK0_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x818) /* TL CORE interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_INT_SET0_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x81C) /* TL_CORE interrupt set register */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_INT_RO0_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x820) /* TL_CORE interrupt indicater status */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_INT_SEL0_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x824) /* CE and NFE select signal */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_CFG_CTRL_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x900)  /* tl cfgspace control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_CFG_PF_EN_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x904) /* PF SUPPORT ENABLE */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_PORT_USED_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x908) /* PORT used indicator */
#define CSR_HIPCIEC50_TL_CORE_REG_PN_PF_STR_IDX0_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x910) /* port physical function start number */
#define CSR_HIPCIEC50_TL_CORE_REG_PN_PF_STR_IDX1_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x914) /* port physical function start number */
#define CSR_HIPCIEC50_TL_CORE_REG_PN_PF_STR_IDX2_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x918) /* port physical function start number */
#define CSR_HIPCIEC50_TL_CORE_REG_PN_PF_STR_IDX3_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x91C) /* port physical function start number */
#define CSR_HIPCIEC50_TL_CORE_REG_PN_PF_STR_IDX4_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x920) /* port physical function start number */
#define CSR_HIPCIEC50_TL_CORE_REG_CFG_PF_VF_CTRL_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x924) /* Cfgspace PF and VF control register */
#define CSR_HIPCIEC50_TL_CORE_REG_PF_FLR_INT_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x940) /* PF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_REG_PF_FLR_INT_STATUS_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x944) /* PF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_REG_PF_FLR_EN_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x948) /* Enable PF  level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID0_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x94C)  /* vf virtio device id */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID1_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x950)  /* vf virtio device id */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID2_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x954)  /* vf virtio device id */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID3_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x958)  /* vf virtio device id */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID4_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x95C)  /* vf virtio device id */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID5_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x960)  /* vf virtio device id */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID6_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x964)  /* vf virtio device id */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID7_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x968)  /* vf virtio device id */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_VENDOR_ID0_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x96C)  /* vf virtio vendor id */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_VENDOR_ID1_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x970)  /* reserved */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_CLASS_CODE0_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x974) /* vf nvme class code */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_CLASS_CODE1_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x978) /* reserved */
#define CSR_HIPCIEC50_TL_CORE_REG_VF_CLASS_CODE2_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x97C) /* reserved */
#define CSR_HIPCIEC50_TL_CORE_REG_CFG_FLR_DISABLE_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x980) /* CFGSPACE CAP disable FLR reset */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_0_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA00) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_1_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA04) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_2_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA08) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_3_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA0C) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_4_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA10) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_5_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA14) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_6_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA18) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_7_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA1C) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_8_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA20) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_9_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA24) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_10_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA28) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_11_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA2C) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_12_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA30) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_13_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA34) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_14_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA38) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_15_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA3C) /* TL_TX tag management control */
#define CSR_HIPCIEC50_TL_CORE_REG_CFG_PFN_VF_ONLINE_ST_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA40) /* PFN vf enable interrupt status */
#define CSR_HIPCIEC50_TL_CORE_REG_CFG_PFN_VF_OFFLINE_ST_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA44) /* PFN vf disable interrupt status */
#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_ECO_REG \
    (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xFFC) /* Add some registers for eco. */

/* HIPCIEC50_TL_CORE_PF_REG Base address of Module's Register */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_BASE (0x31000)

/* **************************************************************************** */
/*                      HIPCIEC50_TL_CORE_PF_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_TL_CORE_PF_REG_TL_CFG_PF_FUNC_SEL_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x0) /* PF Function select 0 */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_TL_CFGSPACE_SEL_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x4) /* Select CFGSPACE Function */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_TL_PF_VF_CFGSPACE_SEL_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x8) /* Select VF or PF CFGSPACE Function */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR0_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x10) /* Physical function n BAR0 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR1_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x14) /* Physical function n BAR1 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR2_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x18) /* Physical function n BAR2 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR3_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x1C) /* Physical function n BAR3 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR4_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x20) /* Physical function n BAR4 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR5_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x24) /* Physical function n BAR5 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_ROM_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x28) /* Physical function n extended ROM mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BARN_ENABLE_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x2C) /* Physical function n BAR enable */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR0_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x30) /* Virtual function n BAR0 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR1_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x34) /* Virtual function n BAR1 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR2_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x38) /* Virtual function n BAR2 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR3_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x3C) /* Virtual function n BAR3 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR4_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x40) /* Virtual function n BAR4 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR5_MASK_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x44) /* Virtual function n BAR5 mask */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BARN_ENABLE_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x48) /* Virtual function n BAR enable */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_MSIX_CONTROL_REG_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x50) /* MSIX CONTROL REGISTER */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_MSIX_OFFSET_BIR_REG_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x54) /* MSIX OFFSET AND BIR REGISTER */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PBA_OFFSET_BIR_REG_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x58) /* PBA OFFSET AND BIR REGISTER */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_ARI_NEXT_ADDR_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x60) /* PF0 and PF1 VF ARI next address */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_VF_VENDOR_ID_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x64) /* VF Vendor ID of PF0 and PF1 */
#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_VF_TPH_ST_REG \
    (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x68) /* VF TPH CAP st_mode_sel、st_table_size fields */

/* HIPCIEC50_TL_CORE_VF_REG Base address of Module's Register */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_BASE (0x3A000)

/* **************************************************************************** */
/*                      HIPCIEC50_TL_CORE_VF_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_0_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_1_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_2_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_3_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_4_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x10) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_5_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x14) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_6_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x18) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_7_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_8_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x20) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_9_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x24) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_10_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x28) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_11_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x2C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_12_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x30) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_13_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x34) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_14_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x38) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_15_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x3C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_16_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x40) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_17_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x44) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_18_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x48) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_19_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_20_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x50) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_21_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x54) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_22_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x58) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_23_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_24_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x60) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_25_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x64) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_26_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x68) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_27_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x6C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_28_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x70) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_29_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x74) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_30_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x78) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_31_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x7C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_32_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x80) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_33_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x84) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_34_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x88) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_35_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_36_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x90) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_37_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x94) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_38_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x98) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_39_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_40_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xA0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_41_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xA4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_42_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xA8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_43_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xAC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_44_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xB0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_45_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xB4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_46_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xB8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_47_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xBC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_48_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xC0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_49_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xC4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_50_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xC8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_51_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xCC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_52_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xD0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_53_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xD4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_54_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xD8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_55_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xDC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_56_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xE0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_57_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xE4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_58_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xE8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_59_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xEC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_60_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xF0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_61_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xF4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_62_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xF8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_63_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xFC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_64_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x100) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_65_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x104) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_66_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x108) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_67_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x10C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_68_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x110) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_69_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x114) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_70_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x118) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_71_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x11C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_72_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x120) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_73_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x124) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_74_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x128) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_75_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x12C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_76_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x130) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_77_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x134) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_78_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x138) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_79_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x13C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_80_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x140) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_81_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x144) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_82_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x148) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_83_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x14C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_84_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x150) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_85_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x154) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_86_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x158) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_87_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x15C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_88_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x160) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_89_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x164) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_90_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x168) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_91_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x16C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_92_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x170) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_93_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x174) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_94_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x178) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_95_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x17C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_96_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x180) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_97_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x184) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_98_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x188) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_99_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x18C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_100_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x190) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_101_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x194) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_102_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x198) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_103_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x19C) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_104_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1A0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_105_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1A4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_106_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1A8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_107_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1AC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_108_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1B0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_109_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1B4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_110_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1B8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_111_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1BC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_112_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1C0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_113_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1C4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_114_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1C8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_115_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1CC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_116_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1D0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_117_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1D4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_118_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1D8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_119_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1DC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_120_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1E0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_121_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1E4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_122_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1E8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_123_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1EC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_124_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1F0) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_125_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1F4) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_126_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1F8) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_127_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1FC) /* VF FLR occur interrupt mask */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_0_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x400) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_1_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x404) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_2_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x408) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_3_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x40C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_4_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x410) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_5_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x414) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_6_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x418) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_7_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x41C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_8_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x420) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_9_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x424) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_10_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x428) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_11_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x42C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_12_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x430) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_13_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x434) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_14_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x438) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_15_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x43C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_16_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x440) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_17_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x444) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_18_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x448) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_19_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x44C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_20_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x450) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_21_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x454) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_22_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x458) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_23_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x45C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_24_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x460) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_25_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x464) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_26_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x468) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_27_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x46C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_28_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x470) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_29_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x474) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_30_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x478) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_31_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x47C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_32_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x480) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_33_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x484) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_34_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x488) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_35_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x48C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_36_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x490) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_37_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x494) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_38_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x498) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_39_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x49C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_40_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4A0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_41_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4A4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_42_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4A8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_43_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4AC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_44_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4B0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_45_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4B4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_46_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4B8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_47_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4BC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_48_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4C0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_49_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4C4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_50_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4C8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_51_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4CC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_52_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4D0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_53_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4D4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_54_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4D8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_55_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4DC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_56_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4E0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_57_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4E4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_58_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4E8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_59_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4EC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_60_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4F0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_61_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4F4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_62_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4F8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_63_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4FC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_64_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x500) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_65_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x504) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_66_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x508) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_67_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x50C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_68_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x510) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_69_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x514) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_70_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x518) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_71_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x51C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_72_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x520) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_73_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x524) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_74_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x528) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_75_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x52C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_76_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x530) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_77_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x534) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_78_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x538) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_79_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x53C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_80_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x540) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_81_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x544) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_82_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x548) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_83_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x54C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_84_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x550) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_85_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x554) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_86_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x558) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_87_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x55C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_88_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x560) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_89_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x564) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_90_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x568) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_91_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x56C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_92_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x570) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_93_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x574) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_94_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x578) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_95_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x57C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_96_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x580) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_97_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x584) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_98_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x588) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_99_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x58C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_100_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x590) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_101_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x594) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_102_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x598) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_103_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x59C) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_104_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5A0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_105_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5A4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_106_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5A8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_107_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5AC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_108_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5B0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_109_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5B4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_110_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5B8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_111_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5BC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_112_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5C0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_113_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5C4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_114_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5C8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_115_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5CC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_116_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5D0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_117_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5D4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_118_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5D8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_119_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5DC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_120_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5E0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_121_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5E4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_122_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5E8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_123_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5EC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_124_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5F0) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_125_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5F4) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_126_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5F8) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_127_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5FC) /* VF FLR occur interrupt status */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_0_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x800) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_1_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x804) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_2_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x808) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_3_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x80C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_4_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x810) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_5_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x814) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_6_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x818) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_7_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x81C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_8_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x820) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_9_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x824) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_10_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x828) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_11_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x82C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_12_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x830) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_13_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x834) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_14_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x838) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_15_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x83C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_16_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x840) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_17_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x844) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_18_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x848) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_19_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x84C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_20_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x850) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_21_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x854) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_22_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x858) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_23_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x85C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_24_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x860) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_25_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x864) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_26_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x868) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_27_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x86C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_28_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x870) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_29_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x874) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_30_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x878) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_31_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x87C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_32_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x880) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_33_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x884) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_34_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x888) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_35_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x88C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_36_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x890) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_37_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x894) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_38_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x898) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_39_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x89C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_40_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8A0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_41_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8A4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_42_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8A8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_43_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8AC) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_44_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8B0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_45_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8B4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_46_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8B8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_47_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8BC) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_48_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8C0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_49_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8C4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_50_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8C8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_51_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8CC) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_52_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8D0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_53_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8D4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_54_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8D8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_55_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8DC) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_56_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8E0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_57_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8E4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_58_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8E8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_59_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8EC) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_60_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8F0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_61_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8F4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_62_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8F8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_63_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8FC) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_64_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x900) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_65_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x904) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_66_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x908) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_67_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x90C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_68_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x910) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_69_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x914) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_70_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x918) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_71_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x91C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_72_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x920) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_73_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x924) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_74_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x928) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_75_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x92C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_76_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x930) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_77_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x934) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_78_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x938) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_79_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x93C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_80_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x940) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_81_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x944) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_82_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x948) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_83_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x94C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_84_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x950) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_85_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x954) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_86_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x958) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_87_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x95C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_88_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x960) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_89_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x964) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_90_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x968) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_91_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x96C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_92_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x970) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_93_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x974) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_94_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x978) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_95_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x97C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_96_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x980) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_97_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x984) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_98_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x988) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_99_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x98C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_100_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x990) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_101_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x994) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_102_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x998) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_103_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x99C) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_104_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9A0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_105_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9A4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_106_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9A8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_107_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9AC) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_108_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9B0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_109_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9B4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_110_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9B8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_111_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9BC) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_112_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9C0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_113_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9C4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_114_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9C8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_115_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9CC) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_116_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9D0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_117_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9D4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_118_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9D8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_119_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9DC) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_120_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9E0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_121_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9E4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_122_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9E8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_123_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9EC) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_124_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9F0) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_125_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9F4) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_126_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9F8) /* Enable VF level reset as SPEC description */
#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_127_REG \
    (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9FC) /* Enable VF level reset as SPEC description */

/* HIPCIEC50_TL_CORE_CC_REG Base address of Module's Register */
#define CSR_HIPCIEC50_TL_CORE_CC_REG_BASE (0x3C000)

/* **************************************************************************** */
/*                      HIPCIEC50_TL_CORE_CC_REG Registers' Definitions                            */
/* **************************************************************************** */


/* HIPCIEC50_TL_CORE_DFX_REG Base address of Module's Register */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE (0x3E000)

/* **************************************************************************** */
/*                      HIPCIEC50_TL_CORE_DFX_REG Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ASYN_FIFO_ST_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x0) /* TL TX asynchronous FIFO Status */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_INGRESS_EGRESS_CNT_CTRL_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x4) /* TL TX ingress and egress TLP count control */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_INGRESS_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x8) /* TL_TX CH0 receive TLP counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CTRL_EGRESS_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xC) /* TL_TX CTRL transmit TLP counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_SCH_FIFO_ST_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x10) /* TL TX_ST FIFO status */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CTRL_HS_ST_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x14) /* TL TX_CTRL with DL handshake status */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ECC_CFG_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x30) /* TL TX SRAM ECC configure */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ECC_ERR_ADDR_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x34) /* TL TX SRAM ECC  error, the SRAM address */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ECC_1BIT_ERR_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x38) /* TL TX 1bit ECC Error counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ECC_2BIT_ERR_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x3C) /* TL TX 2bit ECC Error counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ERR_ERROR_STATUS_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x40) /* TL TX ERR ERROR STATUS */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_CNT_CTRL_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x50) /* Traffic monitor control */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ECRC_ERR_INSERT_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x54) /* TL_TX ECRC error insert counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CNT_ST_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x58) /* Traffic monitor status */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_0_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x60) /* TL TX capture or insert field in TLP, The DW0 field of header */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_1_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x64) /* TL TX capture or insert field in TLP, The DW1 field of header */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_2_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x68) /* TL TX capture or insert field in TLP, The DW2 field of header */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_3_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x6C) /* TL TX capture or insert field in TLP, The DW3 field of header */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_MAP_0_REG                                                     \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x70) /* TL TX capture or insert field in TLP, The DW0 field mask of header \
                                                 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_MAP_1_REG                                                     \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x74) /* TL TX capture or insert field in TLP, The DW1 field mask of header \
                                                 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_MAP_2_REG                                                     \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x78) /* TL TX capture or insert field in TLP, The DW2 field mask of header \
                                                 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_MAP_3_REG                                                     \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x7C) /* TL TX capture or insert field in TLP, The DW3 field mask of header \
                                                 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_HED_0_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x80) /* TL TX have capture header DW0 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_HED_1_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x84) /* TL TX have capture header DW1 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_HED_2_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x88) /* TL TX have capture header DW2 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_HED_3_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x8C) /* TL TX have capture header DW3 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CFG_FIFO_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x98) /* TL_TX CFG FIFO read counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_MEM_RD_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x9C) /* TL TX memory read  counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_MEM_WR_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xA0) /* TL TX memory write counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_IO_RD_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xA4) /* TL TX IO read counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_IO_WR_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xA8) /* TL TX IO write counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_MSG_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xAC) /* TL TX  message counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ERR_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xB0) /* TL TX CPL counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ATOMIC_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xB8) /* TL TX atomic counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_P2P_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xBC) /* TL TX peer2peer TLP counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_GEN_CPL_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xC0) /* TL TX native gen CPL counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ATOMIC_BLK_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xC8) /* TL TX atomic block error counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_PFX_BLK_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xCC) /* TL TX prefix block error counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_POISON_BLK_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xD0) /* TL TX poison block error counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_FUN_TLP_TLP_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xD4) /* TL TX function TLP number counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_FUN_PAYLOAD_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xD8) /* TL TX function TLP payload counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_FUN_ALL_DW_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xDC) /* TL TX function TLP ALL DW counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_FIFO_STS_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xE4) /* TL TX FIFO empty and full */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_DFX_CTRL_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x100) /* TL_TX_CONTEXT DFX control signals */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_DW0_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x104) /* TL_TX_CONTEXT entry DW 0 info */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_DW1_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x108) /* TL_TX_CONTEXT entry DW 0 info */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_DW2_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x10C) /* TL_TX_CONTEXT entry DW 0 info */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_DW3_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x110) /* TL_TX_CONTEXT entry DW 0 info */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_DW4_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x114) /* TL_TX_CONTEXT entry DW 0 info */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_ERR_INFO_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x118) /* TL_TX_CONTEXT entry err info */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_ERR_STATUS_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x11C) /* TL_TX_CONTEXT DFX control signals */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_CHECH_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x120) /* TL_TX_CONTEXT check request counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_CHECK_UC_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x124) /* TL_TX_CONTEXT check UC counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_CHECK_MALFORM_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x128) /* TL_TX_CONTEXT check malform counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_CHECK_MERGE_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x12C) /* TL_TX_CONTEXT check merge counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_TOUT_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x130) /* TL_TX_CONTEXT CPL timeout counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_SEL_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x300) /* TL RX ODR_CTRL ptr DFX of port select */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P0_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x304) /* TL RX ODR_CTRL ptr DFX of port0 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P1_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x308) /* TL RX ODR_CTRL ptr DFX of port1 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P2_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x30C) /* TL RX ODR_CTRL ptr DFX of port2 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P3_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x310) /* TL RX ODR_CTRL ptr DFX of port3 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P4_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x314) /* TL RX ODR_CTRL ptr DFX of port4 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P5_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x318) /* TL RX ODR_CTRL ptr DFX of port5 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P6_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x31C) /* TL RX ODR_CTRL ptr DFX of port6 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P7_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x320) /* TL RX ODR_CTRL ptr DFX of port7 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P8_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x324) /* TL RX ODR_CTRL ptr DFX of port8 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P9_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x328) /* TL RX ODR_CTRL ptr DFX of port9 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P10_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x32C) /* TL RX ODR_CTRL ptr DFX of port10 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P11_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x330) /* TL RX ODR_CTRL ptr DFX of port11 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P12_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x334) /* TL RX ODR_CTRL ptr DFX of port12 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P13_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x338) /* TL RX ODR_CTRL ptr DFX of port13 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P14_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x33C) /* TL RX ODR_CTRL ptr DFX of port14 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P15_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x340) /* TL RX ODR_CTRL ptr DFX of port15 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_CTRL_IDLE_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x344) /* TL_RX_DFX_ODR_CTRL_IDLE */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_QUEUE_IDLE_P0P3_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x348)
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_QUEUE_IDLE_P4P7_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x34C)
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_QUEUE_IDLE_P8P11_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x350)
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_QUEUE_IDLE_P12P15_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x354)
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_SDAP_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x380) /* RX and AP interface tlp counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_CNT_DFX0_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x384) /* TL RX COUNTER0 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_CNT_DFX1_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x388) /* TL RX COUNTER1 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_0_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x400) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_1_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x404) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_2_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x408) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_3_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x40C) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_4_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x410) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_5_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x414) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_6_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x418) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_7_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x41C) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_8_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x420) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_9_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x424) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_10_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x428) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_11_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x42C) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_12_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x430) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_13_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x434) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_14_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x438) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_15_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x43C) /* TL RX_BUF DFX */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_BUF_PTR_DFX_SEL_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x440) /* TL RX_BUF PTR type select */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_16_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x444) /* TL_RX_DFX_BUF_16 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_17_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x448) /* TL_RX_DFX_BUF_17 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_18_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x44C) /* TL_RX_DFX_BUF_18 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_19_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x450) /* TL_RX_DFX_BUF_19 */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_ECC_ERR_INJECT_CFG_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x500) /* TL RX ECC insert error configuration */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_ECC_ERR_ADDR_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x504) /* TL_RX_ECC_ERR_ADDR */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_ECC_1BIT_ERR_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x508) /* TL RX ECC 1bit error counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_ECC_2BIT_ERR_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x50C) /* TL RX ECC 2bit error counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_INSERT_UNCOR_ERR_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x600) /* tl aer insert uncorable error */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_INSERT_COR_ERR_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x604) /* tl aer insert corable error */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_HEADER_DW0_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x608) /* The information of tl AER insert DW0 header */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_HEADER_DW1_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x60C) /* The information of tl AER insert DW1 header */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_HEADER_DW2_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x610) /* The information of tl AER insert DW2 header */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_HEADER_DW3_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x614) /* The information of tl AER insert DW3 header */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_FUN_NUM_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x618) /* The function number of tl aer insert tlp */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_CFG_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x640) /* TL CFGSPACE SRAM ECC configure */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_ADDR_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x644) /* TL TX SRAM ECC 1bit error, the SRAM address */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_1BIT_ERR_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x648) /* CFGSPCE_1bit ECC Error counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_2BIT_ERR_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x64C) /* CFGSPACE 2bit ECC Error counter */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_TYPE_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x650) /* CFGSPACE ECC ERROR SRAM SEL */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_ERR_ST_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x654) /* CGFSPACE ECC ERR STATUS */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_HDK_STATUS_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x658) /* CFGSPACE access handshake status */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_CFG_PF_DFX_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x65C) /* CFGSPACE access global pf number and port number map */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_CFG_PORTN_NUM0_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x660) /* CFGSPACE port number map to pf */
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_CFG_PF_AER_DFX_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x66C)
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_TLP_GEN_CPL_CACHE_STS_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x670)
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_TLP_GEN_P_CACHE_STS_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x674)
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_TX_UR_FIFO_STS_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x678)
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_UR_FIFO_STS_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x67C)
#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ASYN_FIFO_CNT_REG \
    (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x680) /* AP2TX ASYN FIFO CNT */

/* HIPCIEC_EPF_CFGSPACE Base address of Module's Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_BASE (0x40000)

/* **************************************************************************** */
/*                      HIPCIEC_EPF_CFGSPACE Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_ID_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x0) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_CMDSTS_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x4) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_CLSREV_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_MISC_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xC) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR0_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x10) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR1_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x14) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR2_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x18) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR3_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1C) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR4_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x20) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR5_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x24) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_CBUS_PTR_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x28) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_SUBSYS_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2C) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_EXPROM_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x30) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_CAPPTR_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x34) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCI_RSVD_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x38) /* reserved */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_INT_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3C) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPF_CFGSPACE_PCIE_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x40) /* This is the pcie capability header register */
#define CSR_HIPCIEC_EPF_CFGSPACE_DEVICE_CAPBILITY_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x44) /* This register describe the device capability */
#define CSR_HIPCIEC_EPF_CFGSPACE_DEVICE_CTRL_STATUS_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x48) /* device control status register */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CAPBILITY_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x4C) /* Link capability register */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CTRL_STATUS_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x50) /* Link control register \
                                                                                              */
#define CSR_HIPCIEC_EPF_CFGSPACE_SLOT_CAPABILITY_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x54) /* Slot capability register */
#define CSR_HIPCIEC_EPF_CFGSPACE_SLOT_CTRL_STATUS_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x58) /* Slot control and status register */
#define CSR_HIPCIEC_EPF_CFGSPACE_ROOT_CTRL_STATUS_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x5C) /* Root control status */
#define CSR_HIPCIEC_EPF_CFGSPACE_ROOT_STATUS_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x60)      /* Root status register */
#define CSR_HIPCIEC_EPF_CFGSPACE_DEVICE_CAPABILITY2_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x64) /* device capability 2 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_DEVICE_CTRL2_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x68) /* Device control register 2 \
                                                                                          */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CAPABILITY2_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x6C) /* Link capability 2 */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CTRL_STATUS2_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x70) /* Link control and status 2 */
#define CSR_HIPCIEC_EPF_CFGSPACE_SLOT_CAP_2_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x74) /* Slot Capabilities 2 Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_SLOT_CTRL_2_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x78) /* Slot Control 2 Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x80)                                            /* MSI control and ID regisiter */
#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_LADDR_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x84) /* MSI low address */
#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_HADDR_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x88) /* MSI uppr address */
#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_DATA_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8C)  /* MSI data register */
#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_MASK_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x90)  /* MSI mask register */
#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_PENDING_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x94) /* MSI pending register */
#define CSR_HIPCIEC_EPF_CFGSPACE_VPD_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x98) /* VPD address and ID regisiter */
#define CSR_HIPCIEC_EPF_CFGSPACE_VPD_CAP_DATA_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x9C)    /* VPD data */
#define CSR_HIPCIEC_EPF_CFGSPACE_MSIX_CAP_HEADER_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xA0) /* MSIX control register \
                                                                                             */
#define CSR_HIPCIEC_EPF_CFGSPACE_MSIX_TABLE_CTRL_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xA4) /* MSIX table control register */
#define CSR_HIPCIEC_EPF_CFGSPACE_MSIX_PBA_CTRL_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xA8) /* MSIX pending bit array control register */
#define CSR_HIPCIEC_EPF_CFGSPACE_PME_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xB0) /* PME capability header and PME control */
#define CSR_HIPCIEC_EPF_CFGSPACE_PME_STATUS_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xB4) /* Power management status register */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_COMMON_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xB8) /* Virtio Common capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_COMMON_BAR_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xBC) /* Virtio Common configuration structure BAR indicator */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_COMMON_OFFSET_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xC0) /* Virtio Common configuration structure offset */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_COMMON_LENGTH_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xC4) /* Virtio Common configuration structure length */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_NOTIFY_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xC8) /* Virtio Notify capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_NOTIFY_BAR_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xCC) /* Virtio Notification structure BAR indicator */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_NOTIFY_OFFSET_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xD0) /* Virtio Notification structure offset */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_NOTIFY_LENGTH_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xD4) /* Virtio Notification structure length */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_NOTIFY_OFF_MULTIPLIER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xD8) /* Virtio Notification structure off multiplier */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_ISR_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xDC) /* Virtio ISR capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_ISR_BAR_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xE0) /* Virtio ISR status structure BAR indicator */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_ISR_OFFSET_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xE4) /* Virtio ISR status structure offset */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_ISR_LENGTH_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xE8) /* Virtio ISR status structure length */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_DEVICE_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xEC) /* Virtio Device Specify  capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_DEVICE_BAR_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xF0) /* Virtio Device Specify  configuration structure BAR indicator */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_DEVICE_OFFSET_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xF4) /* Virtio Device Specify  configuration structure offset */
#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_DEVICE_LENGTH_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xF8) /* Virtio Device Specify  configuration structure length */
#define CSR_HIPCIEC_EPF_CFGSPACE_AER_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x100) /* Advance Error Report capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_UNCR_ERR_STATUS_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x104) /* uncorrectable error status */
#define CSR_HIPCIEC_EPF_CFGSPACE_UNCR_ERR_MASK_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x108) /* uncorrectable error mask */
#define CSR_HIPCIEC_EPF_CFGSPACE_UNCR_ERR_SEVERITY_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x10C) /* uncorrectable error serverity */
#define CSR_HIPCIEC_EPF_CFGSPACE_COR_ERR_STATUS_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x110)                                               /* Correctable error status */
#define CSR_HIPCIEC_EPF_CFGSPACE_COR_ERR_MASK_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x114) /* correctable error mask */
#define CSR_HIPCIEC_EPF_CFGSPACE_ADVACD_CAP_CTRL_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x118) /* advanced error capabilities and control register */
#define CSR_HIPCIEC_EPF_CFGSPACE_FIRST_HEADER_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x11C) /* First DW header log \
                                                                                               */
#define CSR_HIPCIEC_EPF_CFGSPACE_SECOND_HEADER_LOG_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x120)                                                   /* Second DW header log */
#define CSR_HIPCIEC_EPF_CFGSPACE_THIRD_HEADER_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x124) /* Third DW header log \
                                                                                               */
#define CSR_HIPCIEC_EPF_CFGSPACE_FOUR_HEADER_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x128)  /* Forth DW header log */
#define CSR_HIPCIEC_EPF_CFGSPACE_ROOT_ERROR_COMMAND_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x12C) /* Root error report command */
#define CSR_HIPCIEC_EPF_CFGSPACE_ROOT_ERROR_STATUS_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x130) /* Roor Error status */
#define CSR_HIPCIEC_EPF_CFGSPACE_ERR_SOURCE_IDEN_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x134) /* Erorr soure identification register */
#define CSR_HIPCIEC_EPF_CFGSPACE_FIRST_PREFIX_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x138) /* First DW prefix log \
                                                                                               */
#define CSR_HIPCIEC_EPF_CFGSPACE_SECOND_PREFIX_LOG_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x13C)                                                   /* Second DW prefix log */
#define CSR_HIPCIEC_EPF_CFGSPACE_THIRD_PREFIX_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x140) /* Third DW prefix log \
                                                                                               */
#define CSR_HIPCIEC_EPF_CFGSPACE_FOUR_PREFIX_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x144)  /* Forth DW prefix log */
#define CSR_HIPCIEC_EPF_CFGSPACE_ARI_CAP_HEADER_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x150)   /* ARI capability header \
                                                                                               */
#define CSR_HIPCIEC_EPF_CFGSPACE_ARI_CTRL_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x154) /* ARI control and capability */
#define CSR_HIPCIEC_EPF_CFGSPACE_DOE_HED_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1A0)  /* PCI Express Extend CAP Header \
                                                                                       */
#define CSR_HIPCIEC_EPF_CFGSPACE_DOE_CAP_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1A4)  /* DOE capability */
#define CSR_HIPCIEC_EPF_CFGSPACE_DOE_CTRL_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1A8) /* DOE Control Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_DOE_STATUS_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1AC)   /* DOE  Status Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_WR_DATA_MBOX_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1B0) /* write data malibox */
#define CSR_HIPCIEC_EPF_CFGSPACE_RD_DATA_MBOX_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1B4) /* read data mailbox */
#define CSR_HIPCIEC_EPF_CFGSPACE_SRIOV_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x200)                                             /* SRROIOV capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_SRIOV_CAP_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x204)  /* SRROIOV capability */
#define CSR_HIPCIEC_EPF_CFGSPACE_SRIOV_CTRL_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x208) /* SRROIOV control register */
#define CSR_HIPCIEC_EPF_CFGSPACE_INIT_VF_NUMBER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x20C) /* Initial VF and Totla VF */
#define CSR_HIPCIEC_EPF_CFGSPACE_FUNC_DEP_VF_NUM_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x210) /* Function dependency link and VF NUMBER */
#define CSR_HIPCIEC_EPF_CFGSPACE_VF_RID_SETTING_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x214) /* First offset and Stride register */
#define CSR_HIPCIEC_EPF_CFGSPACE_VF_DEVICE_ID_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x218)     /* VF device ID */
#define CSR_HIPCIEC_EPF_CFGSPACE_VF_PAGE_SIZE_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x21C)     /* supported Page Size */
#define CSR_HIPCIEC_EPF_CFGSPACE_SYSTEM_PAGE_SIZE_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x220) /* System page size */
#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR0_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x224) /* Virtual function  Base address 0  register */
#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR1_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x228) /* Virtual function  Base address 1 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR2_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x22C) /* Virtual function  Base address 2 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR3_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x230) /* Virtual function  Base address 3 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR4_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x234) /* Virtual function  Base address 4 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR5_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x238) /* Virtual function  Base address 5 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_VF_MIG_STATE_ARRAY_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x23C) /* VF Migration state array offset */
#define CSR_HIPCIEC_EPF_CFGSPACE_ATS_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x260) /* Address translation service capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_ATS_CAP_CTRL_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x264) /* ATS capability and control register */
#define CSR_HIPCIEC_EPF_CFGSPACE_PR_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x280) /* Page Request capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_PR_CAP_CTRL_STATUS_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x284) /* Page Request capability control and status */
#define CSR_HIPCIEC_EPF_CFGSPACE_PR_OUT_REQ_CAP_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x288) /* outstanding page request capability */
#define CSR_HIPCIEC_EPF_CFGSPACE_PR_OUT_REQ_ALC_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x28C) /* outstanding page request capability */
#define CSR_HIPCIEC_EPF_CFGSPACE_TPH_EXTEND_CAP_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2A0) /* pcie tph extended capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_TPH_REQ_CAP_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2A4) /* tph request capability register */
#define CSR_HIPCIEC_EPF_CFGSPACE_TPH_REQ_CTRL_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2A8) /* tph requester control register */
#define CSR_HIPCIEC_EPF_CFGSPACE_PASID_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2C0) /* PASID capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_PASID_CAP_CTRL_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2C4) /* PASID capability  and control */
#define CSR_HIPCIEC_EPF_CFGSPACE_SECONDARY_PCIE_EXT_CAP_HED_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x310) /* Secondary PCI Express Extended Capability Header */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x314) /* Link Control 3 Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_LANE_ERROR_STATUS_REG_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x318) /* Lane Error Status Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER01_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x31C) /* Link Control 3 Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER23_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x320) /* Link Control 3 Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER45_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x324) /* Link Control 3 Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER67_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x328) /* Link Control 3 Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER89_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x32C) /* Link Control 3 Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER1011_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x330) /* Link Control 3 Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER1213_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x334) /* Link Control 3 Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER1415_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x338) /* Link Control 3 Register */
#define CSR_HIPCIEC_EPF_CFGSPACE_L1PM_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3C0) /* L1 PM substates extended capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_L1PM_CAPABILITY_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3C4) /* L1 PM substates capability register */
#define CSR_HIPCIEC_EPF_CFGSPACE_L1PM_CONTROL1_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3C8) /* L1 PM substates control 1 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_L1PM_CONTROL2_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3CC) /* L1 PM substates control 2 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_L1PM_STATUS_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3D0) /* L1 PM substates status register */
#define CSR_HIPCIEC_EPF_CFGSPACE_DEVICE_SERIAL_NUMBER_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x4E0) /* device serial number extended capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_SERIAL_LNUM_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x4E4) /* serial low number register */
#define CSR_HIPCIEC_EPF_CFGSPACE_SERIAL_HNUM_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x4E8) /* serial high number register */
#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X00_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x500) /* Extend capability register 00 */
#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X04_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x504) /* Extend capability register 04 */
#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X08_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x508) /* Extend capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X0C_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x50C) /* Extend capability register 0c */
#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X10_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x510) /* Extend capability register 10 */
#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X14_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x514) /* Extend capability register 14 */
#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X18_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x518) /* Extend capability register 18 */
#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X1C_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x51C) /* Extend capability register 1c */
#define CSR_HIPCIEC_EPF_CFGSPACE_ACS_CAP_0X00_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x630) /* ACS capability register 00 */
#define CSR_HIPCIEC_EPF_CFGSPACE_ACS_CAP_0X04_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x634) /* ACS capability register 04 */
#define CSR_HIPCIEC_EPF_CFGSPACE_LTR_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x6D0) /* LTR extended capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_LTR_MAX_LATENCY_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x6D4) /* LTR MAX snoop/no snoop latency register */
#define CSR_HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_REG00_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x700) /* DL feature capability register 00 */
#define CSR_HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_REG04_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x704) /* DL feature capability register 04 */
#define CSR_HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_REG08_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x708) /* DL feature capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG00_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x70C) /* RX Margin capability register 00 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG04_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x710) /* RX Margin capability register 04 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_0_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x714) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_1_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x718) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_2_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x71C) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_3_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x720) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_4_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x724) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_5_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x728) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_6_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x72C) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_7_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x730) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_8_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x734) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_9_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x738) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_10_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x73C) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_11_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x740) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_12_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x744) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_13_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x748) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_14_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x74C) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_15_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x750) /* RX Margin capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG00_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x780) /* Gen5 phy capability header */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG04_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x784) /* Gen5 capability register */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG08_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x788) /* Gen5 Control register */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG0C_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x78C) /* Gen5 Status register */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG10_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x790) /* Gen5 Received modify TS Data1 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG14_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x794) /* Gen5 Received modify TS Data2 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG18_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x798) /* Gen5 Transmitted modify TS Data1 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG1C_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x79C) /* Gen5 Transmitted modify TS Data2 register */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG20_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x7A0) /* Gen5 tx preset */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG24_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x7A4) /* Gen5 tx preset */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG28_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x7A8) /* Gen5 tx preset */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG2C_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x7AC) /* Gen5 tx preset */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG00_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x800) /* CCIX transport capability register 00 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG04_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x804) /* CCIX transport capability register 04 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG08_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x808) /* CCIX transport capability register 08 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG0C_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x80C) /* CCIX transport capability register 0C */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG10_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x810) /* CCIX transport capability register 10 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG14_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x814) /* CCIX transport capability register 14 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG18_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x818) /* CCIX transport capability register 18 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG1C_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x81C) /* CCIX transport capability register 1C */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG20_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x820) /* CCIX transport capability register 20 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG24_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x824) /* CCIX transport capability register 24 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG28_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x828) /* CCIX transport capability register 28 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG2C_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x82C) /* CCIX transport capability register 2C */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG30_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x830) /* CCIX transport capability register 30 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG34_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x834) /* CCIX transport capability register 34 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG38_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x838) /* CCIX transport capability register 38 */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG3C_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x83C) /* CCIX transport capability register 3C */
#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG40_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x840) /* CCIX transport capability register 40 */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG00_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x880) /* Gen4 phy txpreset capability register 00 */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG04_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x884) /* reserved */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG08_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x888) /* reserved */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG0C_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x88C) /* gen4 equalization req and status */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG10_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x890) /* local link data parity status */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG14_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x894) /* retimer link data parity status */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG18_REG \
    (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x898) /* second retimer link data parity status */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG1C_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x89C) /* reserved */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG20_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8A0) /* Gen4 tx preset */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG24_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8A4) /* Gen4 tx preset */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG28_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8A8) /* Gen4 tx preset */
#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG2C_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8AC) /* Gen4 tx preset */

/* HIPCIEC_EPFN_CFGSPACE Base address of Module's Register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_BASE (0x40000)

/* **************************************************************************** */
/*                      HIPCIEC_EPFN_CFGSPACE Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_ID_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x0) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_CMDSTS_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x4) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_CLSREV_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x8) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_MISC_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xC) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR0_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x10) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR1_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x14) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR2_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x18) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR3_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x1C) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR4_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x20) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR5_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x24) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_CBUS_PTR_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x28) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_SUBSYS_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2C) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_EXPROM_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x30) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_CAPPTR_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x34) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCI_RSVD_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x38) /* reserved */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_INT_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x3C) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIE_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x40) /* This is the pcie capability header register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DEVICE_CAPBILITY_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x44) /* This register describe the device capability */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DEVICE_CTRL_STATUS_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x48) /* device control status register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_LINK_CAPBILITY_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x4C) /* Link capability register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_LINK_CTRL_STATUS_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x50) /* Link control register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SLOT_CAPABILITY_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x54) /* Slot capability register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SLOT_CTRL_STATUS_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x58) /* Slot control and status register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ROOT_CTRL_STATUS_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x5C) /* Root control status \
                                                                                                */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ROOT_STATUS_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x60) /* Root status register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DEVICE_CAPABILITY2_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x64) /* device capability 2 register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DEVICE_CTRL2_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x68) /* Device control register 2 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_LINK_CAPABILITY2_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x6C) /* Link capability 2 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_LINK_CTRL_STATUS2_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x70) /* Link control and status 2 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SLOT_CAP_2_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x74) /* Slot Capabilities 2 Register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SLOT_CTRL_2_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x78) /* Slot Control 2 Register \
                                                                                           */
#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x80) /* MSI control and ID regisiter */
#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_LADDR_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x84)   /* MSI low address */
#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_HADDR_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x88)   /* MSI uppr address */
#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_DATA_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x8C)    /* MSI data register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_MASK_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x90)    /* MSI mask register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_PENDING_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x94) /* MSI pending register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VPD_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x98) /* VPD address and ID regisiter */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VPD_CAP_DATA_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x9C) /* VPD data */
#define CSR_HIPCIEC_EPFN_CFGSPACE_MSIX_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xA0) /* MSIX control register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_MSIX_TABLE_CTRL_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xA4) /* MSIX table control register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_MSIX_PBA_CTRL_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xA8) /* MSIX pending bit array control register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PME_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xB0) /* PME capability header and PME control */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PME_STATUS_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xB4) /* Power management status register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_COMMON_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xB8) /* Virtio Common capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_COMMON_BAR_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xBC) /* Virtio Common configuration structure BAR indicator */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_COMMON_OFFSET_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xC0) /* Virtio Common configuration structure offset */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_COMMON_LENGTH_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xC4) /* Virtio Common configuration structure length */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_NOTIFY_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xC8) /* Virtio Notify capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_NOTIFY_BAR_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xCC) /* Virtio Notification structure BAR indicator */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_NOTIFY_OFFSET_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xD0) /* Virtio Notification structure offset */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_NOTIFY_LENGTH_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xD4) /* Virtio Notification structure length */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_NOTIFY_OFF_MULTIPLIER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xD8) /* Virtio Notification structure off multiplier */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_ISR_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xDC) /* Virtio ISR capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_ISR_BAR_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xE0) /* Virtio ISR status structure BAR indicator */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_ISR_OFFSET_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xE4) /* Virtio ISR status structure offset */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_ISR_LENGTH_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xE8) /* Virtio ISR status structure length */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_DEVICE_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xEC) /* Virtio Device Specify  capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_DEVICE_BAR_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xF0) /* Virtio Device Specify  configuration structure BAR indicator */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_DEVICE_OFFSET_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xF4) /* Virtio Device Specify  configuration structure offset */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_DEVICE_LENGTH_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xF8) /* Virtio Device Specify  configuration structure length */
#define CSR_HIPCIEC_EPFN_CFGSPACE_AER_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x100) /* Advance Error Report capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_UNCR_ERR_STATUS_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x104) /* uncorrectable error status */
#define CSR_HIPCIEC_EPFN_CFGSPACE_UNCR_ERR_MASK_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x108) /* uncorrectable error mask */
#define CSR_HIPCIEC_EPFN_CFGSPACE_UNCR_ERR_SEVERITY_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x10C) /* uncorrectable error serverity */
#define CSR_HIPCIEC_EPFN_CFGSPACE_COR_ERR_STATUS_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x110) /* Correctable error status */
#define CSR_HIPCIEC_EPFN_CFGSPACE_COR_ERR_MASK_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x114) /* correctable error mask \
                                                                                             */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ADVACD_CAP_CTRL_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x118) /* advanced error capabilities and control register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_FIRST_HEADER_LOG_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x11C) /* First DW header log */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SECOND_HEADER_LOG_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x120) /* Second DW header log */
#define CSR_HIPCIEC_EPFN_CFGSPACE_THIRD_HEADER_LOG_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x124)                                                   /* Third DW header log */
#define CSR_HIPCIEC_EPFN_CFGSPACE_FOUR_HEADER_LOG_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x128) /* Forth DW header log \
                                                                                                */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ROOT_ERROR_COMMAND_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x12C) /* Root error report command */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ROOT_ERROR_STATUS_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x130) /* Roor Error status \
                                                                                                  */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ERR_SOURCE_IDEN_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x134) /* Erorr soure identification register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_FIRST_PREFIX_LOG_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x138) /* First DW prefix log */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SECOND_PREFIX_LOG_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x13C) /* Second DW prefix log */
#define CSR_HIPCIEC_EPFN_CFGSPACE_THIRD_PREFIX_LOG_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x140)                                                   /* Third DW prefix log */
#define CSR_HIPCIEC_EPFN_CFGSPACE_FOUR_PREFIX_LOG_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x144) /* Forth DW prefix log \
                                                                                                */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ARI_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x150)                                            /* ARI capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ARI_CTRL_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x154) /* ARI control and capability \
                                                                                         */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SRIOV_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x200)                                             /* SRROIOV capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SRIOV_CAP_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x204) /* SRROIOV capability */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SRIOV_CTRL_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x208) /* SRROIOV control register \
                                                                                           */
#define CSR_HIPCIEC_EPFN_CFGSPACE_INIT_VF_NUMBER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x20C) /* Initial VF and Totla VF */
#define CSR_HIPCIEC_EPFN_CFGSPACE_FUNC_DEP_VF_NUM_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x210) /* Function dependency link and VF NUMBER */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_RID_SETTING_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x214) /* First offset and Stride register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_DEVICE_ID_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x218) /* VF device ID */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_PAGE_SIZE_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x21C) /* supported Page Size */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SYSTEM_PAGE_SIZE_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x220) /* System page size */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR0_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x224) /* Virtual function  Base address 0  register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR1_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x228) /* Virtual function  Base address 1 register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR2_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x22C) /* Virtual function  Base address 2 register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR3_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x230) /* Virtual function  Base address 3 register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR4_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x234) /* Virtual function  Base address 4 register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR5_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x238) /* Virtual function  Base address 5 register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_MIG_STATE_ARRAY_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x23C) /* VF Migration state array offset */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ATS_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x260) /* Address translation service capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ATS_CAP_CTRL_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x264) /* ATS capability and control register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PR_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x280) /* Page Request capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PR_CAP_CTRL_STATUS_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x284) /* Page Request capability control and status */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PR_OUT_REQ_CAP_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x288) /* outstanding page request capability */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PR_OUT_REQ_ALC_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x28C) /* outstanding page request capability */
#define CSR_HIPCIEC_EPFN_CFGSPACE_TPH_EXTEND_CAP_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2A0) /* pcie tph extended capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_TPH_REQ_CAP_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2A4) /* tph request capability register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_TPH_REQ_CTRL_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2A8) /* tph requester control register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PASID_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2C0) /* PASID capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_PASID_CAP_CTRL_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2C4) /* PASID capability  and control */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DEVICE_SERIAL_NUMBER_CAP_HEADER_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x4E0) /* device serial number extended capability header */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SERIAL_LNUM_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x4E4) /* serial low number register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_SERIAL_HNUM_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x4E8) /* serial high number register */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X00_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x500) /* Extend capability register 00 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X04_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x504) /* Extend capability register 04 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X08_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x508) /* Extend capability register 08 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X0C_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x50C) /* Extend capability register 0c */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X10_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x510) /* Extend capability register 10 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X14_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x514) /* Extend capability register 14 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X18_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x518) /* Extend capability register 18 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X1C_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x51C) /* Extend capability register 1c */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ACS_CAP_0X00_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x630) /* ACS capability register 00 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_ACS_CAP_0X04_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x634) /* ACS capability register 04 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DL_FEATURE_CAP_REG00_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x700) /* DL feature capability register 00 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DL_FEATURE_CAP_REG04_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x704) /* DL feature capability register 04 */
#define CSR_HIPCIEC_EPFN_CFGSPACE_DL_FEATURE_CAP_REG08_REG \
    (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x708) /* DL feature capability register 08 */

/* HIPCIEC_EVF_CFGSPACE Base address of Module's Register */
#define CSR_HIPCIEC_EVF_CFGSPACE_BASE (0x40000)

/* **************************************************************************** */
/*                      HIPCIEC_EVF_CFGSPACE Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_ID_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x0) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_CMDSTS_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x4) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_CLSREV_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x8) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_MISC_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xC) /* This register specify the register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR0_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x10) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR1_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x14) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR2_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x18) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR3_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x1C) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR4_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x20) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR5_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x24) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_CBUS_PTR_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x28) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_SUBSYS_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x2C) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_EXPROM_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x30) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_CAPPTR_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x34) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCI_RSVD_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x38) /* reserved */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_INT_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x3C) /* This register specify the base address register of config space. */
#define CSR_HIPCIEC_EVF_CFGSPACE_PCIE_CAP_HEADER_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x40) /* This is the pcie capability header register */
#define CSR_HIPCIEC_EVF_CFGSPACE_DEVICE_CAPBILITY_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x44) /* This register describe the device capability */
#define CSR_HIPCIEC_EVF_CFGSPACE_DEVICE_CTRL_STATUS_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x48) /* device control status register */
#define CSR_HIPCIEC_EVF_CFGSPACE_LINK_CAPBILITY_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x4C) /* Link capability register */
#define CSR_HIPCIEC_EVF_CFGSPACE_LINK_CTRL_STATUS_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x50) /* Link control register \
                                                                                              */
#define CSR_HIPCIEC_EVF_CFGSPACE_SLOT_CAPABILITY_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x54) /* Slot capability register */
#define CSR_HIPCIEC_EVF_CFGSPACE_SLOT_CTRL_STATUS_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x58) /* Slot control and status register */
#define CSR_HIPCIEC_EVF_CFGSPACE_ROOT_CTRL_STATUS_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x5C) /* Roor control status */
#define CSR_HIPCIEC_EVF_CFGSPACE_ROOT_STATUS_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x60)      /* Root status register */
#define CSR_HIPCIEC_EVF_CFGSPACE_DEVICE_CAPABILITY2_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x64) /* device capability 2 register */
#define CSR_HIPCIEC_EVF_CFGSPACE_DEVICE_CTRL2_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x68) /* Device control register 2 \
                                                                                          */
#define CSR_HIPCIEC_EVF_CFGSPACE_LINK_CAPABILITY2_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x6C) /* Link capability 2 */
#define CSR_HIPCIEC_EVF_CFGSPACE_LINK_CTRL_STATUS2_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x70) /* Link control and status 2 */
#define CSR_HIPCIEC_EVF_CFGSPACE_SLOT_CAP_2_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x74) /* Slot Capabilities 2 Register */
#define CSR_HIPCIEC_EVF_CFGSPACE_SLOT_CTRL_2_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x78) /* Slot Control 2 Register */
#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_CAP_HEADER_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x80)                                            /* MSI control and ID regisiter */
#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_LADDR_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x84) /* MSI low address */
#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_HADDR_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x88) /* MSI uppr address */
#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_DATA_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x8C)  /* MSI data register */
#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_MASK_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x90)  /* MSI mask register */
#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_PENDING_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x94)     /* MSI pending register */
#define CSR_HIPCIEC_EVF_CFGSPACE_MSIX_CAP_HEADER_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xA0) /* MSIX control register \
                                                                                             */
#define CSR_HIPCIEC_EVF_CFGSPACE_MSIX_TABLE_CTRL_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xA4) /* MSIX table control register */
#define CSR_HIPCIEC_EVF_CFGSPACE_MSIX_PBA_CTRL_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xA8) /* MSIX pending bit array control register */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_COMMON_HEADER_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xB8) /* Virtio Common capability header */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_COMMON_BAR_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xBC) /* Virtio Common configuration structure BAR indicator */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_COMMON_OFFSET_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xC0) /* Virtio Common configuration structure offset */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_COMMON_LENGTH_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xC4) /* Virtio Common configuration structure length */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_NOTIFY_HEADER_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xC8) /* Virtio Notify capability header */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_NOTIFY_BAR_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xCC) /* Virtio Notification structure BAR indicator */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_NOTIFY_OFFSET_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xD0) /* Virtio Notification structure offset */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_NOTIFY_LENGTH_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xD4) /* Virtio Notification structure length */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_NOTIFY_OFF_MULTIPLIER_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xD8) /* Virtio Notification structure off multiplier */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_ISR_HEADER_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xDC) /* Virtio ISR capability header */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_ISR_BAR_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xE0) /* Virtio ISR status structure BAR indicator */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_ISR_OFFSET_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xE4) /* Virtio ISR status structure offset */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_ISR_LENGTH_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xE8) /* Virtio ISR status structure length */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_DEVICE_HEADER_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xEC) /* Virtio Device Specify  capability header */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_DEVICE_BAR_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xF0) /* Virtio Device Specify  configuration structure BAR indicator */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_DEVICE_OFFSET_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xF4) /* Virtio Device Specify  configuration structure offset */
#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_DEVICE_LENGTH_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xF8) /* Virtio Device Specify  configuration structure length */
#define CSR_HIPCIEC_EVF_CFGSPACE_AER_CAP_HEADER_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x100) /* Advance Error Report capability header */
#define CSR_HIPCIEC_EVF_CFGSPACE_UNCR_ERR_STATUS_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x104) /* uncorrectable error status */
#define CSR_HIPCIEC_EVF_CFGSPACE_UNCR_ERR_MASK_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x108) /* uncorrectable error mask */
#define CSR_HIPCIEC_EVF_CFGSPACE_UNCR_ERR_SEVERITY_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x10C) /* uncorrectable error serverity */
#define CSR_HIPCIEC_EVF_CFGSPACE_COR_ERR_STATUS_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x110)                                               /* Correctable error status */
#define CSR_HIPCIEC_EVF_CFGSPACE_COR_ERR_MASK_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x114) /* correctable error mask */
#define CSR_HIPCIEC_EVF_CFGSPACE_ADVACD_CAP_CTRL_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x118) /* advanced error capabilities and control register */
#define CSR_HIPCIEC_EVF_CFGSPACE_FIRST_HEADER_LOG_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x11C) /* First DW header log \
                                                                                               */
#define CSR_HIPCIEC_EVF_CFGSPACE_SECOND_HEADER_LOG_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x120)                                                   /* Second DW header log */
#define CSR_HIPCIEC_EVF_CFGSPACE_THIRD_HEADER_LOG_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x124) /* Third DW header log \
                                                                                               */
#define CSR_HIPCIEC_EVF_CFGSPACE_FOUR_HEADER_LOG_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x128)  /* Forth DW header log */
#define CSR_HIPCIEC_EVF_CFGSPACE_FIRST_PREFIX_LOG_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x138) /* First DW prefix log \
                                                                                               */
#define CSR_HIPCIEC_EVF_CFGSPACE_ARI_CAP_HEADER_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x150)   /* ARI capability header \
                                                                                               */
#define CSR_HIPCIEC_EVF_CFGSPACE_ARI_CTRL_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x154) /* ARI control and capability */
#define CSR_HIPCIEC_EVF_CFGSPACE_TPH_EXTEND_CAP_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x2A0) /* pcie tph extended capability header */
#define CSR_HIPCIEC_EVF_CFGSPACE_TPH_REQ_CAP_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x2A4) /* tph request capability register */
#define CSR_HIPCIEC_EVF_CFGSPACE_TPH_REQ_CTRL_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x2A8) /* tph requester control register */
#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X00_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x500) /* Extend capability register 00 */
#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X04_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x504) /* Extend capability register 04 */
#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X08_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x508) /* Extend capability register 08 */
#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X0C_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x50C) /* Extend capability register 0c */
#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X10_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x510) /* Extend capability register 10 */
#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X14_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x514) /* Extend capability register 14 */
#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X18_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x518) /* Extend capability register 18 */
#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X1C_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x51C) /* Extend capability register 1c */
#define CSR_HIPCIEC_EVF_CFGSPACE_ACS_EXT_CAP_HEADER_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x630) /* ACS Extended Capability Header */
#define CSR_HIPCIEC_EVF_CFGSPACE_ACS_CAPABILITY_REG \
    (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x634) /* ACS Capability Register */

#endif
